EP0454352A1
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EP
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Configurable logic array
Assignee: Advanced Micro Devices Inc
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Filing: 1991-04-18
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Granted: —
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Expires: 2011-04-18
Abstract
Abstract A configurable logic array includes an array of configurable logic cells (R₁C₁, ... R₈C₈) arranged in columns and rows. A plurality of input/output cells are arranged around the perimeter of the array, and provide interfaces to input/output pads on the chip. A configurable interconnect structure includes vertical buses (VBUS1, ... VBUS9) between the columns of configurable logic cells, and horizontal buses (HBUS1, ... HBUS5) between the rows of configurable logic cells. Thus, each configurable logic cell in a subset of the array, has four adjacent buses in the interconnect structure. The configurable logic cells in this subset of the array include input structures, having programmable inputs connected to the buses on all four sides of the cell. Also, combinational logic connected to the input structure generates logic signals in response to the selected input signals. Finally, the configurable logic cells include output structures connected to the combinational logic, and having programmable outputs connected to the buses on all four sides of the cell.
Inventors
- 👤 Om Prakash Agrawal
- 👤 Michael James Wright
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
379 words
A configurable logic array, comprising: configuration storage means for storing program data specifying a user defined data processing function; a plurality of configurable logic means CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means; a plurality of input/output means, each coupled to an input/output pad and having an input and an output, for providing interfaces between the respective input/output pads and the respective inputs and outputs; configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and input/output means into logical networks in response to program data in the configuration storage means, wherein the configurable interconnect means includes a set of horizontal buses H i , extending across the array between the rows of configurable logic means, and a set of vertical buses V j , extending across the array between the columns of configurable logic means; wherein each configurable logic means CL c,r in a subset of the configurable logic means includes: input means, having interconnect inputs connected to horizontal buses H r and H r+1 and to vertical buses V c and V c+1 , for supplying input signals selected in response to program data in the configuration storage means from the interconnect inputs; logic means, connected to the input means, for generating logic signals in response to the input signals and program data in the configuration storage means; and output means, connected to the logic means and having interconnect outputs connected to horizontal buses H r and H r+1 and to vertical buses V c and V c+1 , for supplying output signals selected from the logic signals in response to program data in the configuration storage means to the interconnect outputs.
Claim 2
Dependent Claim
87 words
The configurable logic array of claim 1, wherein the output means in each member of the subset of configurable logic means includes a first output macrocell having an interconnect output connected to the horizontal bus H r , a second output macrocell having an interconnect output connected to the vertical bus V c+1 , a third output macrocell having an interconnect output connected to the horizontal bus H r+1 , and a fourth output macrocell having an interconnect output connected to the vertical bus V c .
Claim 3
Dependent Claim
130 words
The configurable logic array of claim 1, wherein the logic means in each member of the subset of configurable logic means includes: first level means for generating logic signals as a function of up to four input signals; second level means for generating logic signals as a function of five input signals; and third level means for generating logic signals as a function of six input signals; and wherein the output means includes: means for selecting independently output signals for each of the interconnect outputs connected to horizontal buses H r and H r+1 and to vertical buses V c and V c+1 , from independent sets of signals, each independent set including logic signals generated by the first level means, the second level means, and the third level means.
Claim 4
Dependent Claim
26 words
The configurable logic array of claim 3, wherein the first level means further includes means for generating logic signals as a function of three input signals.
Claim 5
Dependent Claim
132 words
The configurable logic array of claim 1, wherein the logic means in the subset of configurable logic means includes: means for generating a plurality of intermediate logic signals, wherein each intermediate logic signal in the plurality is a function of a respective independent subset of the input signals; and means, receiving the plurality of intermediate logic signals, for generating a wide-gate logic signal as a function of the plurality of intermediate logic signals; and wherein the output means includes: means for selecting independently output signals for each of the interconnect outputs connected to horizontal buses H r and H r+1 and to vertical buses V c and V c+1 , from independent sets of logic signals, each independent set including logic signals generated by the logic means and the wide-gate logic signal.
Claim 6
Dependent Claim
96 words
The configurable logic array of claim 1, wherein the output means in each member of the subset of configurable logic means includes: means, connected to the logic means and receiving at least one signal from the configurable interconnect means, for selecting independently output signals for each of the interconnect outputs connected to horizontal buses H r and H r+1 and to vertical buses V c and V c+1 , from independent sets of signals, each independent set including logic signals generated by the logic means and the at least one signal from the configurable interconnect means.
Claim 7
Dependent Claim
153 words
The configurable logic array of claim 2, wherein each of the first, second, third and fourth output macrocells comprises: first selecting means, having a plurality of inputs connected to receive logic signals and an output, for selecting one of its plurality of inputs as its output; means, having an input connected to the output of the first selecting means and having an output, for storing a signal supplied to its input for supply to its output; second selecting means, having an input connected to receive a logic signal, having an input connected to the output of the means for storing, and having an output, for selecting a signal at one of its inputs for supply to its output; and buffer means, having an input connected to the output of the second selecting means and an output connected to a respective interconnect output, for driving a signal on its input to the interconnect output.
Claim 8
Dependent Claim
79 words
The configurable logic array of claim 7, wherein the second selecting means includes: a first multiplexer, having an input connected to the output of the means for storing and an input connected to an input of the first selecting means, and having an output; a second multiplexer, having an input connected to the output of the first multiplexer and an input connected to receive a logic signal, and having an output connected to the input of the buffer means.
Claim 9
Dependent Claim
136 words
The configurable logic array of claim 1, wherein horizontal buses H r and H r+1 and vertical buses V c and V c+1 in the configurable interconnect means each include a respective plurality of long lines extending across the array; and wherein the input means in each member of the subset of configurable logic means includes interconnect inputs connected to each long line in the respective pluralities of long lines on horizontal buses H r and H r+1 and on vertical buses V c and V c+1 ; and wherein the output means in each member of the subset of configurable logic means includes interconnect outputs connected to each long line in the respective pluralities of long lines on horizontal buses H r and H r+1 and on vertical buses V c and V c+1 .
Claim 10
Dependent Claim
91 words
The configurable logic array of claim 1, wherein horizontal buses H r and H r+1 and vertical buses V c and V c+1 in the configurable interconnect means each include a respective plurality of uncommitted long lines extending across the array; and wherein the output means in each member of the subset of configurable logic means includes interconnect outputs connected to each uncommitted long line in the respective pluralities of uncommitted long lines on horizontal buses H r and H r+1 and on vertical buses V c and V c+1 .
Claim 11
Dependent Claim
394 words
The configurable logic array of claim 1, wherein the logic means in each member of the subset of configurable logic means includes: first means, connected to receive a first subset of the input signals from the input means, for generating a logic signal in response the first subset and program data in the configuration storage means; second means, connected to receive a second subset of the input signals from the input means, for generating a logic signal in response the second subset and program data in the configuration storage means; third means, connected to receive a third subset of the input signals from the input means, for generating a logic signal in response the third subset and program data in the configuration storage means; fourth means, connected to receive a fourth subset of the input signals from the input means, for generating a logic signal in response the fourth subset and program data in the configuration storage means; and means, connected to receive the logic signals generated in the first, second, third, and fourth means, for generating a logic signal in response to the logic signals generated in the first, second, third, and fourth means, a fifth subset of the input signals and program data in the configuration storage means; and wherein the input means in each member of the subset of configurable logic means includes: first selecting means, connected to a first subset of the interconnect inputs, for supplying the first subset of the input signals selected from at least the first subset of the interconnect inputs in response to program data in the configuration storage means; second selecting means, connected to a second subset of the interconnect inputs, for supplying the second subset of the input signals selected from at least the second subset of the interconnect inputs in response to program data in the configuration storage means; third selecting means, connected to a third subset of the interconnect inputs, for supplying the third subset of the input signals selected from at least the third subset of the interconnect inputs in response to program data in the configuration storage means; fourth selecting means, connected to a fourth subset of the interconnect inputs, for supplying the fourth subset of the input signals selected from at least the fourth subset of the interconnect inputs in response to program data in the configuration storage means.
Claim 12
Dependent Claim
63 words
The configurable logic array of claim 11, wherein the logic means in each member of the subset further includes: means, connected to receive the logic signals generated in the first, second, third, and fourth means, for generating a logic signal in response to the logic signals generated in the first, second, third, and fourth means, and program data in the configuration storage means.
References Cited (Backward Citations)
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