Linear array wafer scale integration architecture

Claim 2

A cell structure suitable for use in a cellular array, the cell being formed to have N bounda­ries, each boundary having input and output bus means for respectively communicating signals and first and second adjacent boundaries, the cell structure compris­ing: selection means associated with each boundary and having plural selection inputs, coupled to receive the input bus means and the output bus means of the associated boundary, and a selection output, the selec­tion output of N-1 of the boundaries being coupled to the output bus means of the corresponding first adjacent boundary, the selection means being operable to select between the input bus means and the output bus means; logic means coupled between a the remaining one of the selection means and the output bus means of the corresponding adjacent boundary, the logic means being configured and constructed to perform logic func­tions; and control means operably coupled to each of the selection means for causing at each selection means selection of one of the plural selection inputs.

Claim 3

The architecture of claim 1, the control means including power-up means operable to cause each of the selection means to select the corresponding out­put bus means for communication to the selection output.

Claim 4

The architecture of claim 1, including OPEN signals associated with each of the boundaries, and means responsive to assertion of any one of the OPEN signals to cause the corresponding selection means to select the input bus means for communication to the selection output.

Claim 5

A plurality of integrated circuit cells of substantially identical construction formed on a semiconductor wafer, each of the cells being formed to have N boundaries, each boundary having input and output bus means for respectively receiving signals thereat and first and second adjacent boundaries, the integra­ted circuit cells each further comprising: plural selection means, each associated with a corresponding one of the boundaries, and having at least a pair of selection inputs coupled to receive the input bus means and the output bus means of the associated boundary, and a selection output, the selection means being operable to select between the input bus means and the output bus means for communication to the selec­tion output; logic means coupled between the selection output of a one of the selection means and the output bus means of a boundary adjacent the boundary associa­ted with the one selection means, the remaining selection means having their selection outputs coupled to the output bus means of the boundary adjacent to the boundary associated with such remaining selection means, the logic means being configured and constructed to perform logic functions; and control means operably coupled to each of the selection means for causing at each selection means selection of one of the plural selection inputs.

Claim 6

A plurality of integrated circuit cells of substantially identical construction formed on a semiconductor wafer, each of the cells being formed to have N boundaries, each boundary having input and output bus means for respectively receiving signals thereat and first and second adjacent boundaries, the integra­ted circuit cells each further comprising: plural selection means, each associated with a corresponding one of the boundaries, and having at least a pair of selection inputs coupled to receive the input bus means and the output bus means of the associated boundary, and a selection output, the selection means being operable to select between the input bus means and the output bus means for communication to the selec­tion output; logic means coupled between the selection output of a one of the selection means and the output bus means of a boundary adjacent the boundary associa­ted with the one selection means, the remaining selection means having their selection outputs coupled to the output bus means of the boundary adjacent to the boundary associated with such remaining selection means, the logic means being configured and constructed to perform logic functions; and control means operably coupled to each of the selection means for causing at each selection means selection of one of the plural selection inputs.

Claim 7

The plurality of integrated circuit cells of claim 4, wherein each of the integrated circuit cells is oriented so that opposing boundaries of the integrated circuit cell are rotated 180 degrees relative to any adjacent integrated circuit cell.

Claim 8

The plurality of integrated circuit cells of claim 5, the control means including power-up means operable to cause each of the selection means to select the corresponding output bus means for communication to the selection output.

Claim 9

The plurality of integrated circuit cells of claim 4, including OPEN signals associated with each of the boundaries of each of the integrated circuit cells, and means responsive to assertion of any one of the OPEN signals to cause the corresponding selection means to select the input bus means for communication to the selection output.

Claim 10

The plurality of integrated circuit cells of claim 7, wherein each of the integrated circuit cells includes means for generating the OPEN signals, and means for communicating the generated OPEN signals to each neighboring integrated circuit cell.

Claim 11

Apparatus formed on a wafer of semicon­ductor material, the apparatus comprising an array of substantially configured cells containing logic circuitry, the array containing periphery cells defining the periph­ery of the array, and interior cells defining the remain­ing cells of the array, each of the cells having at least one neighbor cell adjacent thereto, each of the cells further comprising: a boundary between the cell and each neighbor cell adjacent thereto; input and output bus means associated with each boundary for communicating signals from and to the neighbor cell adjacent such bound­ary, respectively; selection means for communicating signals from the input bus means associated with a selected one of the boundaries to the logic circuitry; means for communicating output data signals from the logic circuitry to the output bus means associated with a one of the bounda­ries, and to the selection means; the selection means including means for receiv­ing the output data signals from the logic circuitry and for communicating the output data signals to the output bus means associated with other of the boundaries; and wherein each cell of the array is formed on the wafer rotated 180 degrees relative to any neighbor cell thereto.

Claim 12

Apparatus formed on a wafer of semicon­ductor material, the apparatus comprising an array of substantially configured cells containing logic circuitry, the array containing periphery cells defining the periph­ery of the array, and interior cells defining the remain­ing cells of the array, each of the cells having at least one neighbor cell adjacent thereto, each of the cells further comprising: a boundary between the cell and each neighbor cell adjacent thereto; input and output bus means associated with each boundary for communicating signals from and to the neighbor cell adjacent such bound­ary, respectively; selection means for communicating signals from the input bus means associated with a selected one of the boundaries to the logic circuitry; means for communicating output data signals from the logic circuitry to the output bus means associated with a one of the bounda­ries, and to the selection means; the selection means including means for receiv­ing the output data signals from the logic circuitry and for communicating the output data signals to the output bus means associated with other of the boundaries; and wherein each cell of the array is formed on the wafer rotated 180 degrees relative to any neighbor cell thereto.

Claim 13

The apparatus of claim 9, including means for logically connecting the logic circuitry of the certain ones of the cells in a linear array.

Claim 14

The apparatus of claim 10, wherein the logical connection of the linear array by the connect­ing means incorporates use of the selection means of adjacent cells of the array.

Claim 15

The apparatus of claim 11, wherein the logical connection of the cells of the linear array produces a signal delay between the logic circuitry of any adjacent cell that is substantially identical.