Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Claim 2

A configurable logic array, comprising: configuration storage means for storing program data specifying a user defined data processing function; a plurality of configurable logic means CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the conf igurable logic means CL c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means; a plurality of conf igurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means; configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means; wherein the configurable interconnect means is symmetrically disposed relative to the inputs and outputs of configurable logic means.

Claim 3

The configurable logic array of claim 1, wherein the configurable interconnect means includes means for directly connecting one output of configurable logic means CL c,r to one input of sconfigurable logic means CL c+2,r ; and means for directly connecting one output of configurable logic means CL c,r to one input of configurable logic means CL c,r+2 .

Claim 4

The configurable logic array of claim 1, wherein the configurable interconnect means includes a plurality of horizontal buses HB i , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB j , for j equal to 1 to C+1, along the columns of the array, so that each of the plurality of configurable logic means has four adjacent buses in the configurable interconnect means, and wherein each of the plurality of configurable logic means has at least one output coupled to each of the four adjacent buses.

Claim 5

The configurable logic array of claim 1, wherein the configurable interconnect means includes a plurality of horizontal buses HB i , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB j , for j equal to 1 to C+1, along the columns of the array, so that each of the plurality of configurable logic means has four adjacent buses in the configurable interconnect means, and wherein each of the plurality of configurable logic means has at least one input coupled to each of the four adjacent buses.

Claim 6

The configurable logic array of claim 1, wherein the configurable interconnect means includes a plurality of horizontal buses HB i , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB j , for j equal to 1 to C+1, along the columns of the array, so that each of the plurality of configurable logic means has four adjacent buses in the configurable interconnect means, and wherein each of the plurality of configurable logic means has at least one output coupled to each of the four adjacent buses and at least one input coupled to each of the four adjacent buses.

Claim 7

The configurable logic array of claim 1, wherein the configurable interconnect means includes: means for directly connecting a subset of the plurality of outputs of a given configurable logic means to inputs of eight other configurable logic means in the array.

Claim 8

The configurable logic array of claim 1, wherein the configurable interconnect means includes: a plurality of horizontal buses HB i , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB j for j equal to 1 to C+1, along the columns of the array, and further includes: a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory; the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB j , and a second end connected to a horizontal connection of a switching matrix at the intersection with another vertical bus VB k , and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory; the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB i , and a second end connected to a vertical connection of a switching matrix at the intersection with another horizontal bus HB m , and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory; and configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

Claim 9

The configurable logic array of claim 1, wherein the configurable interconnect means includes: a plurality of horizontal buses HB i , along the rows in the array, and a plurality of vertical buses VB j along the columns of the array so that there is a bus on four sides of each configurable logic means, each bus including a control line extending across the array; a first plurality of programmable interconnect points, each connected to the control line in a given bus, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory; a second plurality of interconnect points, each connected to the control line in a given bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the respective control line; means for driving a control signal to a conducting line; and a plurality of configurable control line driving means, one for each horizontal bus and one for each vertical bus, and each configurable control line driving means coupled to the control line in a respective bus and to the conducting line, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration memory.

Claim 10

The configurable logic array of claim 1, wherein the configurable interconnect means includes: a plurality of horizontal buses HB i , along the rows in the array, and a plurality of vertical buses VB j , along the columns of the array, each vertical and horizontal bus including a control line extending across the array; a first plurality of programmable interconnect points, each connected to the control line in a given bus, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory; a second plurality of interconnect points, each connected to the control line in a given bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the respective control line; first means for driving a control signal to a first conducting line; second means for driving a control signal to a second conducting line; a first plurality of configurable control line driving means, one for each horizontal bus, and each coupled to the control line in a respective horizontal bus and to the first conducting line, for driving a signal from the control line in the respective horizontal bus to the first conducting line, or for driving a signal from the first conducting line to the control line in the respective horizontal bus, in response to program data in the configuration memory; and a second plurality of configurable control line driving means, one for each vertical bus, and each coupled to the control line in a respective vertical bus and to the second conducting line, for driving a signal from the control line in the respective vertical bus to the second conducting line, or for driving a signal from the second conducting line to the control line in the respective vertical bus, in response to program data in the configuration memory.

Claim 11

The configurable logic array of claim 1, wherein the configurable interconnect means includes means for directly connecting one output of configurable logic means CL c,r to one input of configurable logic means CL c+2,r ; means for directly connecting one output of configurable logic means CL c,r to one input of configurable logic means CL c,r+2 ; and means for directly connecting one output of configurable logic means CL c,r to one input of configurable logic means CL c-2,r ; and means for directly connecting one output of configurable logic means CL c,r to one input of configurable logic means CL c,r-2 .

Claim 12

A configurable logic array, comprising: configuration storage means for storing program data specifying a user defined data processing function; a plurality of configurable logic means CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the row 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signalsMsupplied to the respective plurality of inputs and in response to program data in the configuration storage means; a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means; and configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means; wherein at least one of the configurable input/output means includes: a tristate buffer means, having an output connected to the configurable interconnect means, supplying an output ssignal or presenting a high impedance state at its output in response to a tristate control signal; and means for supplying the tristate control signal in response to program data in the configuration storage means.

Claim 13

A configurable logic array, comprising: configuration storage means for storing program data specifying a user defined data processing function; a plurality of configurable logic means CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the row 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signalsMsupplied to the respective plurality of inputs and in response to program data in the configuration storage means; a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means; and configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means; wherein at least one of the configurable input/output means includes: a tristate buffer means, having an output connected to the configurable interconnect means, supplying an output ssignal or presenting a high impedance state at its output in response to a tristate control signal; and means for supplying the tristate control signal in response to program data in the configuration storage means.

Claim 14

The configurable logic array of claim 11. wherein each configurable input/output means in a subset of the plurality of configurable input/output means includes a storage element having an input and an output, and further including means, coupled to the storage elements in the subset of configurable input/output means and to the configuration storage means, for connecting the output of the storage element in a first selected configurable input/output means in the subset to the input of the storage element in a second selected configurable input/output means in the subset in response to program data in the configuration storage means.

Claim 15

The configurable logic array of claim 11, wherein each configurable input/output means in a subset of the plurality of configurable input/output means includes a storage element having an input and an output, and further including: means, coupled to the storage elements in the configurable input/output means in the suhset and to the sconfiguration storage means, for connecting the input of the storage element in a selected configurable input/output means in the subset to the configurable interconnect means, and for connecting the output of the storage element in the selected configurable input/output means in the subset to the configurable interconnect means, in response to program data in the configuration storage means.

Claim 16

The configurable logic array of claim 11, wherein each configurable input/output means in a subset of the plurality of configurable input/output means includes a storage element having an input and an output, and further including: means, coupled to the storage elements in the subset of configurable input/output means and to the configuration storage means, for connecting the input of the storage element in a selected configurable input/output means in the subset to the configurable interconnect means, and for connecting the output of, the storage element in the selected configurable input/output means in the subset to the respective input/output pad, in response to program data in the configuration storage means.

Claim 17

The configurable logic array of claim 11 wherein at least one of the configurable input/output means includes: a first storage element, having an input and an output and receiving a first clock signal, for storing data from sits input in response to the first clock signal for supply to its output; a second storage element, having an input and an output and receiving a second clock signal, for storing data from its input in response to the second clock signal for supply to its output; and means, coupled to the first and second storage elements, to the respective input/output pad and to the configurable interconnect means, for connecting the respective input/output pad to the input of the first storage element, the output of the first storage element to the input of the second storage element, and the output of the second storage element to the configurable interconnect means.

Claim 18

A configurable input/output cell providing configurable interconnection between an adjacent input/output pad and a configurable logic array including an array of configurable logic cells, a programmable interconnect, and a configuration memory storing program data for configuring logical networks in the configurable logic array, comprising: first tristate buffer means, having a data input, a control input, and an output connected to the adjacent input/output pad, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a tristate control signal from the control input; and a first programmable interconnect point, coupled to the control input of the first tristate buffer means and to the programmable interconnect, for supplying the tristate control signal in response to program data in the configuration memory; first means, coupled to the programmable interconnect, for supplying a data signal to the data input of the first tristate buffer means; second tristate buffer means, having a data input, a control input, and an output connected to the programmable interconnect, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a second tristate control signal from the control input; a second programmable interconnect point, coupled to the control input of the second tristate buffer means and to the programmable interconnect, for supplying the second tristate control signal in response to program data in the configuration memory; and second means, coupled to the adjacent input/output pad, for supplying a data signal to the data input of the second tristate buffer means.

Claim 19

A configurable input/output cell providing configurable interconnection between an adjacent input/output pad and a configurable logic array including an array of configurable logic cells, a programmable interconnect, and a configuration memory storing program data for configuring logical networks in the configurable logic array, comprising: first tristate buffer means, having a data input, a control input, and an output connected to the adjacent input/output pad, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a tristate control signal from the control input; and a first programmable interconnect point, coupled to the control input of the first tristate buffer means and to the programmable interconnect, for supplying the tristate control signal in response to program data in the configuration memory; first means, coupled to the programmable interconnect, for supplying a data signal to the data input of the first tristate buffer means; second tristate buffer means, having a data input, a control input, and an output connected to the programmable interconnect, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a second tristate control signal from the control input; a second programmable interconnect point, coupled to the control input of the second tristate buffer means and to the programmable interconnect, for supplying the second tristate control signal in response to program data in the configuration memory; and second means, coupled to the adjacent input/output pad, for supplying a data signal to the data input of the second tristate buffer means.

Claim 20

The configurable input/output meas of claim 16, further including: a first storage element, having a data input, a clock input and an output, for storing data From its data input for supply to its output, in response to a clock signal at its clock input; and a second storage element, having a data input, a clock input and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; means, coupled to the adjacent input/output pad, for supplying a signal to the data input of the first storage element; means, coupled to the programmable interconnect, for supplying a signal to the data input of the second storage element; and wherein the first means for supplying includes a first selecting means, having a plurality of inputs and an output connected to the data input of the first tristate buffer means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the first storage element and the adjacent input/output pad; and the second means for supplying includes a second selecting means, having a plurality of inputs and an output connected to the data input of the second tristate buffer means,for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the second storage element and the programmable interconnect.

Claim 21

The configurable input/output means of claim 16, further including: a storage element, having a data input, a clock input and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; and means, coupled to the adjacent input/output pad, for supplying a signal to the data input of the storage element; and wherein the first means for supplying includes a first selecting means, having a plurality of inputs and an output connected to the data input of the first tristate buffer means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the storage element and the adjacent input/output pad.

Claim 22

The configurable input/output means of claim 16, further including: a storage element, having a data input, a clock input and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; and means, coupled to the programmable interconnect, for supplying a signal to the data input of the storage element; and wherein the second means for supplying includes a second selecting means, having a plurality of inputs and an output connected to the data input of the second tristate buffer means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the storage element and the programmable interconnect.

Claim 23

A plurality of configurable input/output cells providing configurable interconnection between adjacent input/output pads and a configurable logic array including an array of configurable logical cells, a programmable interconnect, and a configuration memory storing program data for configuring logical networks in the configurable logic array, each cell in the plurality comprising: array output means, having a data input and an output connected to the adjacent input/output pad, for supplying data from the data input to its output; and first means, coupled to the programmable interconnect, for supplying a data signal to the data input of the array output means; array input means, having a data input and an output connected to the programmable interconnect, for supplying data From the data input to its output; second means, coupled to the adjacent input/output pad, for supplying a data signal to the data input of the array input means; a first storage element, having a data input, a clock sinput and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; and a second storage element, having a data input, a clock input and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; third means, coupled to the programmable interconnect, for supplying a signal to the data input of the first storage element; fourth means, coupled to the adjacent input/output pad, for supplying a signal to the data input of the second storage element; and wherein the first means for supplying includes an array output selecting means, having a plurality of inputs and an output connected to the data input of the array output means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the first storage element, the output of the second storage element and the programmable interconnect; and the second means for supplying includes an array input selecting means, having a plurality of inputs and an output connected to the data input of the array input means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the first storage element, the output of the second storage element and the adjacent input/output pad.

Claim 24

A plurality of configurable input/output cells providing configurable interconnection between adjacent input/output pads and a configurable logic array including an array of configurable logical cells, a programmable interconnect, and a configuration memory storing program data for configuring logical networks in the configurable logic array, each cell in the plurality comprising: array output means, having a data input and an output connected to the adjacent input/output pad, for supplying data from the data input to its output; and first means, coupled to the programmable interconnect, for supplying a data signal to the data input of the array output means; array input means, having a data input and an output connected to the programmable interconnect, for supplying data From the data input to its output; second means, coupled to the adjacent input/output pad, for supplying a data signal to the data input of the array input means; a first storage element, having a data input, a clock sinput and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; and a second storage element, having a data input, a clock input and an output, for storing data from its data input for supply to its output, in response to a clock signal at its clock input; third means, coupled to the programmable interconnect, for supplying a signal to the data input of the first storage element; fourth means, coupled to the adjacent input/output pad, for supplying a signal to the data input of the second storage element; and wherein the first means for supplying includes an array output selecting means, having a plurality of inputs and an output connected to the data input of the array output means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the first storage element, the output of the second storage element and the programmable interconnect; and the second means for supplying includes an array input selecting means, having a plurality of inputs and an output connected to the data input of the array input means, for selecting a signal from one of its plurality of inputs for supply to its output, its plurality of inputs including the output of the first storage element, the output of the second storage element and the adjacent input/output pad.

Claim 25

The configurable input/output cell of claim 20, wherein the configurable logic array further includes a second plurality of configurable input output cells, the configurable input/output cells in the second plurality each comprising: first tristate buffer means, having a data input, a control input, and an output connected to the adjacent input/output pad, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a tristate control signal from the control input; and a first programmable interconnect point, coupled to the control input of the first tristate buffer means and to the programmable interconnect, for supplying the tristate control signal in response to program data in the configuration memory; first means, coupled to the programmable interconnect, for supplying a data signal to the data input of the first tristate buffer means; second tristate buffer means, having a data input, a control input, and an output connected to the programmable interconnect, for buffering data from the data input to its output or presenting a high impedance state to its output in response to a second tristate control signal from the control input; a second programmable interconnect point, coupled to the control input of the second tristate buffer means and to the programmable interconnect, for supplying the second tristate control signal in response to program data in the configuration memory; and second means, coupled to the adjacent input/output pad, for supplying a data signal to the data input of the second tristate buffer means.

Claim 26

A configurable logic element coupled to a configuration memory including a plurality of storage elements storing program data specifying a user defined data processing function, comprising: input means for supplying a set of K input signals; multiplexing means, coupled to the input means and a first set of storage elements in the configuration memory, for selecting a set of P signals from the first set of storage elements, in response to a first subset of the set of K input signals; output means, coupled to the multiplexing means, for selecting a first subset from the set of P signals as element output signals; wherein the configurable logic element has a first side coupled with a first bus, a second side coupled with a second bus, a third side coupled with a third bus, and a fourth side coupled with a fourth bus, and wherein the output means includes: means, coupled to the first, second, third and fourth buses and to the configuration memory, for supplying the element output signals to selected lines on the first, second, third and fourth buses in response to the program data in the configuration memory.

Claim 27

A configurable logic element coupled to a configuration memory including a plurality of storage elements storing program data specifying a user defined data processing function, comprising: input means for supplying a set of K input signals; multiplexing means, coupled to the input means and a first set of storage elements in the configuration memory, for selecting a set of P signals from the first set of storage elements, in response to a first subset of the set of K input signals; output means, coupled to the multiplexing means, for selecting a first subset from the set of P signals as element output signals; wherein the configurable logic element has a first side coupled with a first bus, a second side coupled with a second bus, a third side coupled with a third bus, and a fourth side coupled with a fourth bus, and wherein the output means includes: means, coupled to the first, second, third and fourth buses and to the configuration memory, for supplying the element output signals to selected lines on the first, second, third and fourth buses in response to the program data in the configuration memory.

Claim 28

The configurable logic element of claim 22, wherein the input means includes: means, coupled to the first, second, third and fourth buses and to the configuration memory, for selecting a subset of the set of K input signals from signals on selected lines on the first, second, third and fourth buses in response to the program data in the configuration memory.

Claim 29

The configurable logic element of claim 22, further including means for supplying a plurality of output enable signals, and wherein the means for supplying the element output signals includes: a plurality of tristate output buffers, connected to the selected lines of the first, second, third and fourth buses, and receiving respective ones of the element output signals and respective output enable signals, for supplying the respective ones of the element output signals as output or presenting a high impedance state, in response to the respective output enable signals.

Claim 30

The configurable logic element of claim 22, further including means for supplying a plurality of output enable signals, and wherein the means for supplying the element output signals includes: a plurality of tristate output buffers, connected to the selected lines of the first, second, third and fourth buses, and receiving respective ones of a first set of the element output signals and respective output enable signals, for supplying the respective ones of the first set of the element output signals as output or presenting a high impedance state, in response to the respective output enable signals; and a plurality of direct output buffers receiving respective ones of a second set of the element output signals, for supplying the respective ones as output one respective ones of the first, second, third and fourth buses.

Claim 31

The configurable logic element of claim 22, wherein the element is coupled with a plurality of buses, and wherein the means for supplying includes: a plurality of configurable output cells, at least one cell coupled to each of the first, second, third and fourth buses, and each cell comprising: first selecting means, connected to receive a second subset of the set of P signals, and to the configuration memory, for selecting a first signal; storage means, connected to receive the first signal and a clock signal, for storing the first signal in response to the clock signal and supplying a stored signal; second selecting means, connected to receive the stored signal and a third subset of the set of P signals, for selecting at least one element output signal; and buffering means, connected to receive the at least one element output signal from the second selecting means and to one of the plurality of buses, for driving, the at least one element output signal on the one bus.

Claim 32

The configurable logic element of claim 26, wherein the second selecting means in the output logic cells further include means, coupled to the input means, for selecting a feedback signal for supply as one of the set of K input signals.

Claim 33

The configurable logic element of claim 27, wherein the feedback signal is also an element output signal.

Claim 34

29 The configurable logic element of claim 26, wherein the configuration memory includes means for loading the program data in an initialize mode, and wherein the first selecting means in the output cells include means, coupled to the means for loading and responsive to the initialize mode, for selecting a signal from the means for loading as the first signal to preload the storage means with program data.

Claim 35

The configurable logic element of claim 26, further including means for supplying an output enable signals, and wherein the buffering means includes: a tristate output buffer receiving a selected element output signal and the output enable signal, for supplying the selected element output signal as output on one line of the one bus or presenting a high impedance state in response to the output enable signal; and a direct output buffer receiving a selected element output

Claim 36

A configurable logic element coupled to a configuration memory including a plurality of storage elements storing program data specifying a user defined data processing function, comprising: input means for supplying a set of K input signals; multiplexing means, coupled to the input means and a first set of storage elements in the configuration memory, for selecting a set of P signals and a set of Q signals from the first set of storage elements, in response to a first subset of the set of K input signals; special output means, coupled to the multiplexing means and a second set of storage elements in the configuration memory, for selecting a special output signal from the second set of storage elements in response to the set of Q signals; output means, coupled to the multiplexing means and the special output means, for selecting a first subset from the set of P signals and the special output signal, as element output signals.

Claim 37

A configurable logic element coupled to a configuration memory including a plurality of storage elements storing program data specifying a user defined data processing function, comprising: input means for supplying a set of K input signals; multiplexing means, coupled to the input means and a first set of storage elements in the configuration memory, for selecting a set of P signals and a set of Q signals from the first set of storage elements, in response to a first subset of the set of K input signals; special output means, coupled to the multiplexing means and a second set of storage elements in the configuration memory, for selecting a special output signal from the second set of storage elements in response to the set of Q signals; output means, coupled to the multiplexing means and the special output means, for selecting a first subset from the set of P signals and the special output signal, as element output signals.

Claim 38

The configurable logic element of claim 31, wherein the configurable logic element has a first side coupled with a first bus, a second side coupled with a second bus, a third side coupled with a third bus, and a fourth side coupled with a fourth bus, and wherein the input means includes: means, coupled to the first, second, third and fourth buses and to the configuration memory, for selecting the first subset of the set of K input signals from signals on selected lines on the first, second, third and fourth buses in response to the program data in the configuration memory.