EP0746105A2
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Programmable array clock/reset resource
Assignee: International Business Machines Corp
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Filing: 1996-05-07
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Granted: —
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Expires: 2016-05-07
Abstract
Abstract A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.
Inventors
- 👤 Frederick Curtis Furtek
- 👤 Frank Ray Keyser Iii
- 👤 Scott Whitney Gould
- 👤 Brian A. Worth
- 👤 Terrance John Zittritsch
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 16:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1774; H03K19/1733; H03K19/1737; H03K19/17704
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
166 words
A signal distribution architecture for a programmable array having a plurality of logic cells, the signal distribution architecture comprising a clock/reset distribution network including: a first programmable multiplexer for selecting a first group clock/reset signal for a first group of logic cells of the plurality of logic cells, the first group clock/reset signal being selected from a plurality of system clock/reset signals; a second programmable multiplexer for selecting a second group clock/reset signal for a second group of logic cells of the plurality of logic cells, the second group clock/reset signal being selected from the plurality of system clock/reset signals; and a third programmable multiplexer for selecting a sub-group clock/reset signal for a sub-group of logic cells of one of the first and second groups of logic cells, the sub-group clock/reset signal being selected from a plurality of group clock/reset signals including at least the first and second group clock/reset signals, the sub-group clock/reset signal being available to logic cells of the sub-group of logic cells.
Claim 2
Dependent Claim
133 words
The signal distribution architecture of claim 1 further comprising a reset/clock distribution network including: a first programmable multiplexer for selecting a first group reset/clock signal for the first group of logic cells, the first group reset/clock signal being selected from a plurality of system reset/clock signals; a second programmable multiplexer for selecting a second group reset/clock signal for the second group of logic cells, the second group reset/clock signal being selected from the plurality of system reset/clock signals; and a third programmable multiplexer for selecting a sub-group reset/clock signal for the sub-group of logic cells, the sub-group reset/clock signal being selected from a plurality of group reset/clock signals including at least the first and second group reset/clock signals, the sub-group reset/clock signal being available to logic cells of the sub-group of logic cells.
Claim 3
Dependent Claim
39 words
The signal distribution architecture of claim 2 wherein the plurality of logic cells is arranged into rows and columns of logic cells, and wherein the first and second groups of logic cells each comprise a column of logic cells.
Claim 4
Dependent Claim
139 words
The signal distribution architecture of claim 1 wherein at least one of the programmable multiplexers comprises: an output; a plurality of inputs; a plurality of input buffers, each input buffer of the plurality of input buffers having an input connected to a respective one of the plurality of inputs of the at least one programmable multiplexer, each input buffer of the plurality of input buffers further having an output; and a plurality of programmable elements, each programmable element of the plurality of programmable elements including: a first current carrying terminal connected to the output of a respective one of the plurality of input buffers, and a second current carrying terminal for providing a selected signal to the output of the at least one programmable multiplexer, such that the selected signal is re-driven through the at least one programmable multiplexer.
Claim 5
Dependent Claim
78 words
The signal distribution architecture of claim 4 wherein each input buffer of the plurality of input buffers of the at least one programmable multiplexer comprises an inverter, and wherein the at least one programmable multiplexer further comprises: an output inverter having an input connected to the second current carrying terminal of each programmable element of the plurality of programmable elements, the output inverter further having an output which comprises the output of the at least one programmable multiplexer.
Claim 6
Dependent Claim
33 words
The signal distribution architecture of claim 5 wherein at least one of the plurality of programmable elements of the at least one programmable multiplexer comprises a transmission gate controlled by an SRAM cell.
Claim 7
Dependent Claim
45 words
The signal distribution architecture of claim 1 wherein at least one of the first and second programmable multiplexers includes a constant logic state input and wherein the group clock/reset signal is selected from the plurality of system clock/reset signals and the constant state logic input.
Claim 8
Dependent Claim
49 words
The signal distribution architecture of claim 1 wherein at least one of the first and second programmable multiplexers includes an input derived from an interconnect structure of the programmable array and wherein the group clock/reset signal is selected from the plurality of system clock/reset signals and the derived input.
Claim 9
Dependent Claim
64 words
The signal distribution architecture of claim 1 further comprising: an I/O block for accepting at least one system clock/reset signal of the plurality of system clock/reset signals from an external signal source; and a programmable element connected between the I/O block and the clock/reset distribution network for selectively providing the at least one clock/reset signal to the clock/reset distribution network from the I/O block.
Claim 10
Dependent Claim
150 words
The signal distribution architecture of anyone of claims 1 to 9 wherein the programmable array comprising: a first plurality of logic cells, each logic cell of the first plurality of logic cells including a programmable input multiplexer having a plurality of inputs and an output, a combinatorial logic circuit having an input connected to the output of the programmable input multiplexer, the combinatorial logic circuit further having an output, and a sequential logic circuit having an input connected to the output of the combinatorial logic circuit, the sequential logic circuit further having a clock/reset input; and a programmable clock/reset multiplexer associated with the first plurality of logic cells for providing a selected clock/reset signal to an input of the programmable input multiplexer of each of the first plurality of logic cells and to the clock/reset input of the sequential logic circuit of each of the first plurality of logic cells.
References Cited (Backward Citations)
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