Abstract A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
An apparatus comprising: a plurality of logic regions arranged in an array of rows and columns; a plurality of user-configurable memory blocks included in the array of rows and columns, each of the memory blocks including: (1) a plurality of memory cells that store programming data; (2) an input port configured to receive programming data for each memory cell in the memory block; and (3) an output port to output the received programming data; and programming circuitry coupled to the memory blocks and configured to direct a plurality of programming data elements, each intended to be stored in a target one of the memory cells, through the input and the output ports of selected ones of the plurality of user-configurable memory blocks until each of the programming data elements is stored in its target memory cell.
Claim 2
Independent Claim
136 words
An apparatus comprising: a plurality of logic regions arranged in an array of rows and columns; a plurality of user-configurable memory blocks included in the array of rows and columns, each of the memory blocks including: (1) a plurality of memory cells that store programming data; (2) an input port configured to receive programming data for each memory cell in the memory block; and (3) an output port to output the received programming data; and programming circuitry coupled to the memory blocks and configured to direct a plurality of programming data elements, each intended to be stored in a target one of the memory cells, through the input and the output ports of selected ones of the plurality of user-configurable memory blocks until each of the programming data elements is stored in its target memory cell.
Claim 3
Dependent Claim
20 words
The apparatus of claim 1, wherein the programming circuitry provides the programming data elements to the memory blocks in series.
Claim 4
Dependent Claim
34 words
The apparatus of claim 2, wherein a selected one of the programming data elements passes through the selected ones of the memory blocks until the selected data element arrives at its target memory cell.