US5128559A
Expired / Lapsed
US
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Logic block for programmable logic devices
Assignee: STMicroelectronics lnc USA
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Filing: 1991-08-08
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Granted: 1992-07-07
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Expires: 2011-08-08
Abstract
Abstract A standard logic block, or macrocell, is provided for use on programmable logic devices. The macrocell uses RAM to perform logic functions, and further includes circuitry which allows writing of data to the RAM during use. Each logic block can be configured at programming time to be either a user RAM, allowing the user to write data to such memory during use, or configured as performing logic functions. The contents of macrocells configured as providing logic functions cannot be changed except by reprogramming the device.
Inventors
- 👤 Randy C. Steele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein each column of memory contains 16 bits of storage; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 2
Dependent Claim
158 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein each column of memory contains 16 bits of storage; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 3
Dependent Claim
162 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory columns are capable of being configured to provide a single output; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 4
Dependent Claim
162 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory columns are capable of being configured to provide a single output; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 5
Dependent Claim
187 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory has n columns each having m bits of storage, and wherein said memory columns are capable of being configured as an n output by m bit memory, or as a single output by (n×m) bit memory; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 6
Dependent Claim
187 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, wherein said memory has n columns each having m bits of storage, and wherein said memory columns are capable of being configured as an n output by m bit memory, or as a single output by (n×m) bit memory; a read buffer connected to said random access memory for reading data output therefrom, wherein said read buffer provides a separate read buffer for each memory column; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 7
Dependent Claim
8 words
The circuit block of claim 3, wherein m=16.
Claim 8
Dependent Claim
8 words
The circuit block of claim 4, wherein n=4.
Claim 9
Dependent Claim
24 words
The circuit block of claim 5, wherein said memory columns are further capable of being configured as a 2 output by 32 bit memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |