US5089993A
Expired / Lapsed
US
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Memory module arranged for data and parity bits
Assignee: Texas Instruments Inc
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Filing: 1989-09-29
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Granted: 1992-02-18
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Expires: 2009-09-29
Abstract
Abstract A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. The data memory circuits are arranged to provide a combined data string having a length equal to the sum of the individual data string lengths. Each data memory circuit includes a signal line connected to control transfer of individual data strings. A different data pin is associated with each bit of the combined data string to transfer a datum for output from the memory module. Each signal line is connected to a control pin to receive an external signal for initiating transfer of one of the individual strings from one of the data memory circuits. The module further includes an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines. A first of the additional signal lines is wired in common with the signal line of a first one of the data memory circuits. A second of the additional signal lines is wired in common with the signal line of a second one of the data memory circuits. The additional memory circuit is responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from one of the data memory circuits.
Inventors
- 👤 Joseph H. Neal
- 👤 Kenneth A. Poteet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:08
CPC Classifications
G; G06; G06F; G06F12/00; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/02; G11C5/025; G11C5/06; G11C7/00; G11C7/10; G11C7/1006; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/103; G11C7/1033; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
287 words
A memory module comprising: a plurality of discrete data memory circuits, each organized to provide an individual data string having length equal to an integer multiple of four bits, said data memory circuits arranged to provide a combined data string having a length equal to the sum of the individual data string lengths, each data memory circuit including a signal line connected to control transfer of individual data strings; a plurality of data pins, each associated with a different bit of the combined data string and connected through data lines to transfer a datum, associated with one of the individual data strings, from one of the data memory circuits for output from said memory module; a plurality of control pins with each signal line connected to a control pin to receive an external signal for initiating transfer of one of the individual data strings from one of the data memory circuits; and an additional memory circuit having a plurality of additional signal lines to control transfer of data and a plurality of additional data lines, with a first of the additional signal lines wired in common with the signal line of a first of the data memory circuits to render said additional memory circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the first data memory circuit; and a second of the additional signal lines wired in common with the signal line of a second of the data memory circuits to render said additional memory circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the second data memory circuit.
Claim 2
Dependent Claim
287 words
A memory module comprising: a plurality of discrete data memory circuits, each organized to provide an individual data string having length equal to an integer multiple of four bits, said data memory circuits arranged to provide a combined data string having a length equal to the sum of the individual data string lengths, each data memory circuit including a signal line connected to control transfer of individual data strings; a plurality of data pins, each associated with a different bit of the combined data string and connected through data lines to transfer a datum, associated with one of the individual data strings, from one of the data memory circuits for output from said memory module; a plurality of control pins with each signal line connected to a control pin to receive an external signal for initiating transfer of one of the individual data strings from one of the data memory circuits; and an additional memory circuit having a plurality of additional signal lines to control transfer of data and a plurality of additional data lines, with a first of the additional signal lines wired in common with the signal line of a first of the data memory circuits to render said additional memory circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the first data memory circuit; and a second of the additional signal lines wired in common with the signal line of a second of the data memory circuits to render said additional memory circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the second data memory circuit.
Claim 3
Dependent Claim
34 words
The module of claim 1 wherein all of the data memory circuits are dynamic random access memory circuits and said additional memory circuit includes four signal lines which control the transfer of parity data.
Claim 4
Dependent Claim
30 words
The module of claim 1 wherein the discrete data memory circuits are electrically arranged in pairs to provide a data string length that is an integer multiple of eight bits.
Claim 5
Dependent Claim
83 words
The module of claim 1 wherein the first of the additional signal lines is wired in common with the signal line of a third one of the data memory circuits to provide a data string length that is a multiple of nine bits and wherein the second of the additional signal lines is wired in common with the signal line of a fourth one of the data memory circuits to also provide a data string length that is a multiple of nine bits.
Claim 6
Dependent Claim
24 words
The module of claim 1 wherein there are an equal number of additional signal lines and additional data lines in the additional memory circuit.
Claim 7
Dependent Claim
19 words
The module of claim 1 wherein the number of additional data lines in the additional memory circuit is four.
Claim 8
Dependent Claim
19 words
The module of claim 1 wherein the number of additional signal lines in the additional memory circuit is four.
Claim 9
Dependent Claim
29 words
The module of claim 1 wherein each additional data line is wired to associate a ninth data bit with one string of eight bits in the combined data string.
Claim 10
Dependent Claim
28 words
The module of claim 1 wherein the additional data lines are wired to associate one bit of parity data with every eight bits of the combined data string.
References Cited (Backward Citations)
US4081701A
Cited
US4375665A
Cited
US4583204A
Cited
US4656605A
Cited
US4658377A
Cited
US4636986A
Cited
US4636986B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |