Dynamic memory array with segmented bit lines

Claim 2

A semiconductor memory device comprising: an array of rows and colums of memory cells, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said rows of cells, each cell including storage means coupled to a source-to-drain path of said access transistor, a plurality of bit lines extending along said columns of cells perpendicular to said word lines, a plurality of bit line segments for each of said bit lines, said segments being separate from said bit lines and extending parallel to said bit lines, the source-to-drain paths of said access transistors being connected to said segments, and a plurality of control means, a separate one of said control means being connected between each of said segments and a corresponding one of said bit lines for selectively connecting said segments to a bit line in response to an address.

Claim 3

A device according to claim 1 including a plurality of differential sense amplifiers, each sense amplifier having two inputs, each input coupled to a different one of said bit lines.

Claim 4

A device according to claim 2 including row addressing means for receiving said address and activating said control means; said row addressing means also activating a selected one of said word lines in response to said address.

Claim 5

A device according to claim 2 wherein the capacitance per unit length of said bit lines is much less than that of said segments.

Claim 6

A device according to claim 1 wherein said storage means in each cell is a capacitor.

Claim 7

A device according to claim 1 wherein there are a plurality of said cells connected to each of said segments.

Claim 8

A device according to claim 6 wherein there is at least eight segments per bit line and at least eight cells per segment.

Claim 9

A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in a face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell, a plurality of bit lines extending along said face above said word lines and over said columns of cells, the bit lines being perpendicular to said word lines, a plurality of bit-line segments for each of said bit lines, said segments being separate from said bit lines and extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and a plurality of separate control means, one control means for each of said segments, each of said control means selectively connecting each said segment to a bit line.

Claim 10

A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in a face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell, a plurality of bit lines extending along said face above said word lines and over said columns of cells, the bit lines being perpendicular to said word lines, a plurality of bit-line segments for each of said bit lines, said segments being separate from said bit lines and extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and a plurality of separate control means, one control means for each of said segments, each of said control means selectively connecting each said segment to a bit line.

Claim 11

A device according to claim 8 including a plurality of differential sense amplifiers, one of said sense amplifiers for each column, each sense amplifier having two inputs, each input coupled to a different one of a pair of said bit lines.

Claim 12

A device according to claim 9 including row addressing means for receiving an address and selectively activating said control means in response to said address; said row addressing means also activating a selected one of said word lines in response to said address.

Claim 13

A device according to claim 8 wherein the capacitance per unit length of said bit lines is much less than that of said segments.

Claim 14

A device according to claim 8 wherein said segments are formed by heavily-doped regions in said face.

Claim 15

A device according to claim 8 wherein there is at least eight segments per bit line and at least eight cells per segment.

Claim 16

In a semiconductor memory device: a plurality of memory cells in a column, each cell including an access transistor having a gate, each cell including storage means coupled to a source-to-drain path of said access transistor, a bit line extending along said column of cells, a plurality of bit line segments for said bit line, each of said segments being separate from said bit line and extending parallel to said bit line, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and a plurality of control means, each control means separately and selectively connecting one of said segments to one of said bit lines.

Claim 17

In a semiconductor memory device: a plurality of memory cells in a column, each cell including an access transistor having a gate, each cell including storage means coupled to a source-to-drain path of said access transistor, a bit line extending along said column of cells, a plurality of bit line segments for said bit line, each of said segments being separate from said bit line and extending parallel to said bit line, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and a plurality of control means, each control means separately and selectively connecting one of said segments to one of said bit lines.

Claim 18

A device according to claim 14 including at least two of said bit lines, and a differential sense amplifier having two inputs, each input coupled to one of said two bit lines.

Claim 19

A device according to claim 14 including addressing means for receiving an address and selectively activating said control means; said addressing means also activating a selected one of said gates in response to said address.

Claim 20

A device according to claim 14 wherein the capacitance per unit length of said bit line is much less than that of said segments.

Claim 21

A device according to claim 14 wherein there are at least eight of said segments and at least eight of said cells for each segment.

Claim 22

A device according to claim 14 wherein said storage means in each cell is a capacitor.

Claim 23

A device according to claim 19 wherein said control means are transistors having source-to-drain paths connected to said bit line.