Configurable interconnect structure

Claim 2

The interconnect structure of claim 1, wherein at least one bus includes a conducting uncommitted long line extending across the array, a first plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting respective outputs of logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration store, and a second plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting the uncommitted long line with at least one other bus in response to program data in the configuration store.

Claim 3

A configurable interconnect structure for a configurable logic device, the configurable logic device including a configuration store storing program data specifying a user defined data processing function, an array of configurable logic cells CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic cells CL c,r having a plurality of inputs and outputs, and coupled to the configuration store, and generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration store; a plurality of configurable input/output cells, each coupled to an input/output pad and having an input and an output, and coupled to the configuration store, providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration store; the configurable interconnect structure comprising; a plurality of horizontal buses HB l , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB j , for j equal to 1 to C+1, along the columns of the array; a plurality of switching means at respective intersections of horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration store; the plurality of horizontal buses each including: a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching means at the intersection with vertical bus VB j , and a second end connected to a horizontal connection of a switching means at the intersection with another vertical bus VB k, and each connected to a plurality of interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment, and a plurality of conductive horizontal long lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective horizontal long line in response to program data in the configuration store, and each connected directly to a respective plurality of inputs to configurable logic cells or to input/output cells adjacent to the respective horizontal long line; the plurality of vertical buses each including: a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching means at the intersection with horizontal bus HB l , and a second end connected to a vertical connection of a switching means at the intersection with another horizontal bus HB m, and each connected to a plurality of interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment; a plurality of conductive vertical long lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective vertical long line in response to program data in the configuration store, and each connected directly to a respective plurality of inputs to configurable logic cells or to input/output cells adjacent to the respective long vertical line; and a plurality of programmable interconnect means, at respective intersections of the horizontal and vertical buses, each for interconnecting in response to program data in the configuration store a respective horizontal segment and vertical long line or a respective vertical segment and horizontal long line.

Claim 4

The interconnect structure of claims 1 or 3, wherein at least one of the plurality of horizontal segments has a first end connected to a horizontal connection of a switching means at the intersection with vertical bus VB j , for j equal to 1 through C-1, and a second end connected to a horizontal connection of a switching means at the intersection with vertical bus VB k , where k = j + 2.

Claim 5

The interconnect structure of claims 1 or 3 wherein at least one of the plurality of vertical segments has a first end connected to a vertical connection of a switching means at the intersection with horizontal bus HB j , for j equal to 1 through R-1, and a second end connected to a vertical connection of a switching means at the intersection with horizontal bus HB k , where k = j + 2.

Claim 6

The interconnect structure of claim 3 , wherein at least one bus of the plurality of buses includes a conducting uncommitted long line extending across the array, a first plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration store, and a second plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting the uncommitted long line with another of the plurality of buses in response to program data in the configuration store.

Claim 7

A configurable interconnect structure for a configurable logic device, the configurable logic device including a configuration store storing program data specifying a user defined data processing function, an array of configurable logic cells CL c,r , arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic cells CL c,r having a plurality of inputs and outputs, and coupled to the configuration store, and generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration store; a plurality of configurable input/output cells, each coupled to an input/output pad and having an input and an output, and coupled to the configuration store, providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration store; the configurable interconnect structure comprising: a plurality of horizontal buses HB l , for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB l , for j equal to 1 to C+1, along the columns of the array; a plurality of switching means at respective intersections of horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration store; the plurality of horizontal buses each including: a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching means at the intersection with vertical bus VB j , and a second end connected to a horizontal connection of a switching means at the intersection with another vertical bus VB k, and each connected to a plurality of interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment, and a plurality of conductive horizontal long lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective horizontal long line in response to program data in the configuration store, and each connected directly to a respective plurality of inputs to configurable logic cells or to input/output cells adjacent to the respective horizontal long line; a plurality of conductive uncommitted horizontal lone lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective horizontal uncommitted long line in response to program data in the configuration store; the plurality of vertical buses each including: a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching means at the intersection with horizontal bus HB l , and a second end connected to a vertical connection of a switching means at the intersection with another horizontal bus HB m, and each connected to a plurality of interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment; a plurality of conductive vertical long lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective vertical long line in response to program data in the configuration store, and each connected directly to a respective plurality of inputs to configurable logic cells or to input/output cells adjacent to the respective long vertical line; a plurality of conductive uncommitted vertical long lines, each extending across the array, and each connected to a plurality programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective vertical uncommitted long line in response to program data in the configuration store; a first plurality of programmable interconnect means, at respective intersections of the horizontal and vertical buses, each for interconnecting in response to program data in the configuration store a respective horizontal segment and vertical long line or a respective vertical segment and horizontal long line; and a second plurality of programmable interconnect means, at respective intersections of the horizontal and vertical buses, each for interconnecting in response to program data in the configuration stored a respective horizontal segment and vertical uncommitted long line or a respective vertical segment and horizontal uncommitted long lined.

Claim 8

The interconnect structure of claims 1,3 ,or 7, wherein each member of a subset of the plurality of horizontal segments is connected at the first end to a switching means at the intersection with a vertical bus VB l , and is connected at the second end to a switching means at the intersection with a vertical bus VB m, where m = l + k and k is greater than one.

Claim 9

The interconnect structure of claims 1,3,or 7, wherein each member of a subset of the plurality of vertical segments is connected at the first end to a switching means at the intersection with a horizontal bus HB l , and is connected at the second end to a switching means at the intersection with a horizontal bus HB m , where m = l + k and k is greater than one.

Claim 10

The interconnect structure of claims 1,3,or 7, wherein each horizontal bus includes N horizontal segments, and each member of a subset of the plurality of switching means includes M horizontal connections on a left side of the switching means and M horizontal connections on a right side of the switching means, where M is less than N, and wherein at least N - M horizontal segments through the intersection at which a member of the subset is located spans two or more columns of logic cells.

Claim 11

The interconnect structure of claims 1,3,or 7, wherein each vertical bus includes N vertical segments, and each member of a subset of the plurality of switching means includes M vertical connections on a left side of the switching means and M vertical connections on a right side of the switching means, where M is less than N, and wherein at least N - M vertical segments through the intersection at which a member of the subset is located spans two or more rows of logic cells.

Claim 12

The interconnect structure of claims 1,3,or 7, further including: a horizontal control line extending across the array in each of the horizontal buses; a vertical control line extending across the array in each of the vertical buses; a first plurality of programmable interconnect points, each connected to the control line in a given bus, for interconnecting respective outputs of logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration store; a second plurality of interconnect points, each connected to the control line in a given bus, for interconnecting respective inputs of logic cells and input/output cells adjacent to the control line; means for driving a control signal to a conducting line; and a plurality of configurable control line driving means, each coupled to the control line in a respective bus and to the conducting line, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration store.

Claim 13

The interconnect structure of claims 1,3, or 7, further including: configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration store.

Claim 14

The interconnect structure of claims 1 or 7, further including: configurable repowering means, coupled to at least one vertical segment, configurable for repowering signals on the one vertical segment propagating in a first direction, for repowering signals on the one vertical segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration store.

Claim 15

The interconnect structure of claims 1,3 or 7, wherein the configurable interconnect structure is symmetrically disposed relative to the inputs and outputs of the configurable logic cells.

Claim 16

The interconnect structure of claims 1,3 or 7, wherein the plurality of interconnect points connected to at least one horizontal segment includes a first subset of direct connections to inputs of logic cells and a second subset of programmable interconnect means, coupled to the configuration store, interconnecting respective inputs or outputs of logic cells with respective horizontal segments in response to program data in the configuration store.

Claim 17

The interconnect structure of claims 1,3, or 7, wherein the plurality of interconnect points connected to at least one vertical segment includes a first subset of direct connections to inputs of logic cells and a second subset of programmable interconnect means, coupled to the configuration store, interconnecting respective inputs or outputs of logic cells with respective vertical segments in response to program data in the configuration store.