US5509128A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FPGA architecture including direct logic function circuit to I/O interconnections
Assignee: Microsemi SoC Corp
•
Filing: 1993-10-20
•
Granted: 1996-04-16
•
Expires: 2013-10-20
Abstract
Abstract A user-programmable FPGA architecture includes a plurality of logic function circuits having inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and communicate with I/O pads on the integrated circuit. The I/O modules each include: (1) an input buffer having an input connected to an I/O pad on the integrated circuit and an output connected to an output node, and (2) an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node for placing the output buffer into a high impedance state. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the input nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the control nodes of selected ones of the I/O modules.
Inventors
- 👤 King W. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:43
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/17704
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
430 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an control input node of one of said input/output modules.
Claim 2
Dependent Claim
430 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an control input node of one of said input/output modules.
Claim 3
Dependent Claim
422 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 4
Dependent Claim
422 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 5
Dependent Claim
89 words
The user-programmable FPGA architecture of claim 2 further comprising at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 6
Dependent Claim
91 words
The user-programmable FPGA architecture of claim 2 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 7
Dependent Claim
422 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 8
Dependent Claim
422 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 9
Dependent Claim
91 words
The user-programmable FPGA architecture of claim 5 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules,
Claim 10
Dependent Claim
89 words
The user-programmable FPGA architecture of claim 6 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules,
Claim 11
Dependent Claim
424 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 12
Dependent Claim
424 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 13
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 14
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 15
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 16
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 17
Dependent Claim
453 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 18
Dependent Claim
453 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 19
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuit; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 20
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuit; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 21
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 22
Dependent Claim
451 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 23
Dependent Claim
453 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 24
Dependent Claim
453 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 25
Dependent Claim
452 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect, elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect, elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 26
Dependent Claim
452 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect, elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect, elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules.
Claim 27
Dependent Claim
452 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 28
Dependent Claim
452 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules.
Claim 29
Dependent Claim
454 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 30
Dependent Claim
454 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 31
Dependent Claim
672 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
Claim 32
Dependent Claim
672 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and an input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules; at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said input node of one of said input/output modules; at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an output node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said input of a selected one of said logic function circuits and said output node of one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and one of said second interconnect conductors and at least one direct interconnect conductor connected between an control input node of one of said input/output modules and said one of said second interconnect conductors to form a direct connection path between said output of a selected one of said logic function circuits and said control input node of one of said input/output modules.
References Cited (Backward Citations)
US4717912A
Cited
US4870302A
Cited
US4713557A
Cited
US4706216A
Cited
US4684830A
Cited
US4742252A
Cited
US4870300A
Cited
US5083083A
Cited
US4873459B1
Cited
US4857774A
Cited
US4873459A
Cited
US5046035A
Cited
US5400262A
Cited
US5121394A
Cited
US5132571A
Cited
US5144166A
Cited
US5220213A
Cited
US5122685A
Cited
US5221865A
Cited
US5208491A
Cited
US5220215A
Cited
US5317698A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |