Universal interconnect matrix array

Claim 2

A universal interconnect matrix array comprising: a substrate having a plurality of input/output pads situated along a primary surface of said substrate, data being transmissible to and from the interconnect matrix array only through said input/output pads during normal array operation, said input/output pads being arranged in an area matrix of rows and columns such that at least one of said input/output pads is internal to the input/output pads along the periphery of said area matrix and is connectable to external electronic components; a first set of conductive leads formed across the primary surface in a first direction; a second set of conductive leads formed across the primary surface in a second direction not parallel to said first direction, at least one conductive lead in at least one of said sets of conductive leads being divided into at least two separate conductive segments, selected ones of said conductive leads or segments in both of said sets of conductive leads being connected to at least half of said input/output pads; and means for electrically interconnecting selected ones of said conductive leads or segments in said first set of conductive leads to selected ones of said conductive leads or segments in said second set of conductive leads, wherein: said first set of conductive leads comprises a first plurality of first groups of conductive leads, each of said first groups of conductive leads being located adjacent to a selected row of said input/output pads; and said second set of conductive leads comprises a second plurality of second groups of conductive leads, each of said second groups of conductive leads being located adjacent to a selected column of said input/output pads.

Claim 3

A universal interconnect matrix array comprising: a substrate having a plurality of input/output pads situated along a primary surface of said substrate, data being transmissible to and from the interconnect matrix array only through said input/output pads during normal array operation, said input/output pads being arranged in an area matrix of rows and columns such that at least one of said input/output pads is internal to the input/output pads along the periphery of said area matrix and is connectable to external electronic components; a first set of conductive leads formed across the primary surface in a first direction; a second set of conductive leads formed across the primary surface in a second direction not parallel to said first direction, at least one conductive lead in each of said sets of conductive leads being divided into at least two separate conductive segments, selected ones of said conductive leads or segments in both of said sets of conductive leads being connected to at least half of said input/output pads; and means for electrically interconnecting selected ones of said conductive leads or segments in said first set of conductive leads to selected ones of said conductive leads or segments in said second set of conductive leads, wherein: said first set of conductive leads comprises a first plurality of groups of rows of conductive leads, each of at least two of said groups of rows of conductive leads being located between two adjacent rows of said input/output pads; and said second set of conductive leads comprises a second plurality of groups of columns of conductive leads, each of at least two of said groups of columns of conductive leads being located between two adjacent columns of said input/output pads.

Claim 4

A universal interconnect matrix array comprising: a substrate having a plurality of input/output pads situated along a primary surface of said substrate, data being transmissible to and from the interconnect matrix array only through said input/output pads during normal array operation, said input/output pads being arranged in an area matrix of rows and columns such that at least one of said input/output pads is internal to the input/output pads along the periphery of said area matrix and is connectable to external electronic components; a first set of conductive leads formed across the primary surface in a first direction; a second set of conductive leads formed across the primary surface in a second direction not parallel to said first direction, at least one conductive lead in each of said sets of conductive leads being divided into at least two separate conductive segments, selected ones of said conductive leads or segments in both of said sets of conductive leads being connected to at least half of said input/output pads; and means for electrically interconnecting selected ones of said conductive leads or segments in said first set of conductive leads to selected ones of said conductive leads or segments in said second set of conductive leads, wherein: said first set of conductive leads comprises a first plurality of groups of rows of conductive leads, each of at least two of said groups of rows of conductive leads being located between two adjacent rows of said input/output pads; and said second set of conductive leads comprises a second plurality of groups of columns of conductive leads, each of at least two of said groups of columns of conductive leads being located between two adjacent columns of said input/output pads.

Claim 5

Structure as in claim 2, wherein said input/output pads are connected across said substrate predominantly to selected ones of said conductive leads or segments in both of said sets of conductive leads.

Claim 6

Structure as in claim 2, wherein said input/output pads are connected across said substrate only to selected ones of said conductive leads or segments in both of said sets of conductive leads.

Claim 7

Structure as in claim 2, wherein said means for electrically interconnecting comprises electrically programmable elements.

Claim 8

A crosspoint switch formed as an integrated circuit dedicated for programmably interconnecting electronic components external to the integrated circuit, the crosspoint switch comprising: a substrate having a primary surface; a plurality of input/output pads situated along the primary surface for connection to said external electronic components, said input/output pads being arranged in an area matrix of rows and columns such that at least one of said input/output pads is internal to the input/output pads along the periphery of said area matrix and is connectable to external electronic components; a first set of conductive leads formed across the primary surface in a first direction; a second set of conductive leads formed across the primary surface in a second direction substantially different from the first direction, at least one conductive lead in at least one of said sets of conductive leads being divided into at least two separate conductive segments, selected ones of said conductive leads or segments in both sets of conductive leads being connected to said input/output pads; and means for programmably interconnecting selected ones of said conductive leads or segments in said first set of conductive leads to selected ones of said conductive leads or segments in said second set of conductive leads, wherein: said first set of conductive leads comprises a first plurality of groups of rows of conductive leads, each of at least two of said groups of rows of conductive leads being located between two adjacent rows of said input/output pads; and said second set of conductive leads comprises a second plurality of groups of columns of conductive leads, each of at least one of said groups of columns of conductive leads being located between two adjacent columns of said input/output pads.

Claim 9

A crosspoint switch formed as an integrated circuit dedicated for programmably interconnecting electronic components external to the integrated circuit, the crosspoint switch comprising: a substrate having a primary surface; a plurality of input/output pads situated along the primary surface for connection to said external electronic components, said input/output pads being arranged in an area matrix of rows and columns such that at least one of said input/output pads is internal to the input/output pads along the periphery of said area matrix and is connectable to external electronic components; a first set of conductive leads formed across the primary surface in a first direction; a second set of conductive leads formed across the primary surface in a second direction substantially different from the first direction, at least one conductive lead in at least one of said sets of conductive leads being divided into at least two separate conductive segments, selected ones of said conductive leads or segments in both sets of conductive leads being connected to said input/output pads; and means for programmably interconnecting selected ones of said conductive leads or segments in said first set of conductive leads to selected ones of said conductive leads or segments in said second set of conductive leads, wherein: said first set of conductive leads comprises a first plurality of groups of rows of conductive leads, each of at least two of said groups of rows of conductive leads being located between two adjacent rows of said input/output pads; and said second set of conductive leads comprises a second plurality of groups of columns of conductive leads, each of at least one of said groups of columns of conductive leads being located between two adjacent columns of said input/output pads.