US4479088A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer including test lead connected to ground for testing networks thereon
Assignee: Unisys Corp
•
Filing: 1981-01-16
•
Granted: 1984-10-23
•
Expires: 2001-01-16
Abstract
Abstract Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12', exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.
Inventors
- 👤 Herbert Stopper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:51
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H10P74/27; H10P74/273; H05; H05K; H05K1/00; H05K1/02; H05K1/0286
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
222 words
A wafer having disposed thereon: a plurality of integrated circuit chips having inputs and outputs; a reticulate network formed on said wafer for connecting the output of one of said chips to at least one input of another chip of the wafer; said network including at least one power supply lead and power pad for supplying power to said integrated circuit chips; and said network including a plurality of reticulate logic lines and pad lines, each of said pad lines being connected to a logic input or output point of one of said chips and having a single coupling to one of said logic lines at a position on said wafer, the intercoupling of said logic lines defining the intercoupling connection of chips of the said network, the network further including at least one additional test lead from a terminal of the network to a grounding point on said wafer where contact can be made to ground and adapted to permit resistance testing of the desired intercoupling connection of chips of the said network to which the test lead is connected to determine if the network itself is operational by measurement of the inherent resistance of the line defined as running from said grounding point through said terminal and to one of the input or output points of one of said chips.
Claim 2
Dependent Claim
222 words
A wafer having disposed thereon: a plurality of integrated circuit chips having inputs and outputs; a reticulate network formed on said wafer for connecting the output of one of said chips to at least one input of another chip of the wafer; said network including at least one power supply lead and power pad for supplying power to said integrated circuit chips; and said network including a plurality of reticulate logic lines and pad lines, each of said pad lines being connected to a logic input or output point of one of said chips and having a single coupling to one of said logic lines at a position on said wafer, the intercoupling of said logic lines defining the intercoupling connection of chips of the said network, the network further including at least one additional test lead from a terminal of the network to a grounding point on said wafer where contact can be made to ground and adapted to permit resistance testing of the desired intercoupling connection of chips of the said network to which the test lead is connected to determine if the network itself is operational by measurement of the inherent resistance of the line defined as running from said grounding point through said terminal and to one of the input or output points of one of said chips.
Claim 3
Dependent Claim
69 words
A wafer according to claim 1 wherein said test lead for the network leads from the network to an open grounding point pad disposed on the surface of the wafer at a testing area, which pad is adapted to permit contact to be made with ground during the testing of the network while the input or output point of the chip network line being tested is supplied with power.
Claim 4
Dependent Claim
51 words
A wafer according to claim 1 wherein there are a plurality of test leads, one for each individual logic network, disposed on said wafer enabling testing of said individual logic network for operability in use by measuring the inherent resistance of the line tested and finding it meets expected resistance characteristics.
Claim 5
Dependent Claim
46 words
A wafer according to claim 3 wherein there are a plurality of test leads, one for each logic network connected to their associated grounding points, disposed about the periphery of the wafer and adapted all to be connected to a circumferentially disposed grounding ring during testing.
References Cited (Backward Citations)
GB1305010A
Cited
US3781683A
Cited
US3803483A
Cited
US3789205A
Cited
DE2633175A1
Cited
US4295182A
Cited
US4183460A
Cited
GB2022319A
Cited
US4220917A
Cited
US4241307A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |