Registered logic macrocell with product term allocation and adjacent product term stealing

Claim 2

A macrocell comprising: an OR gate; means for coupling an external signal to a first input to the OR gate; a register means; means for receiving a product term; means having two programmable states for coupling the product term (a) to a second input to the OR gate when in a first programmable state and (b) to the register means when in a second programmable state, and for additionally coupling said product term to an alternate output of said macrocell when in a predetermined one of said first and second programmable states, said alternate output thereby functioning as an expander; and means for programmably coupling the output of the OR gate to the input to an OR gate in a second macrocell.

Claim 3

The macrocell of claim 1, wherein the register means includes a D flip-flop.

Claim 4

The macrocell of claim 1, wherein the register means includes a T flip-flop.

Claim 5

The macrocell of claim 1, wherein the register means includes: a first multiplexer having a product term as a first input and a sum of product terms as a second input; a second multiplexer having a product term as a first input, a static LOW as a second input, the output of the register as a third input, and the inverted output of the register as a fourth input; and an EXCLUSIVE-OR gate having a first input from the output of said first multiplexer and a second input from the output of said second multiplexer, and having its output coupled to the input to the register.

Claim 6

The macrocell of claim 1, wherein the register means includes a multiplexer for selecting between a product term or an external clock signal for driving a clock input to the register.

Claim 7

The macrocell of claim 1, wherein the means includes means for using a product term to enable the register.

Claim 8

The macrocell of claim 1, wherein the register means includes means for using a product term for presetting the register.

Claim 9

The macrocell of claim 1, wherein the register means includes means for using a product term to clear the register.

Claim 10

The macrocell of claim 1, wherein the means for programmably coupling the output of the OR gate to the input to an OR gate in a second macrocell includes a static architecture bit.

Claim 11

The macrocell of claim 1, wherein the means having two programmable states for coupling the product term to a second input to the OR gate when in a first programmable state and (b) the register means when in a second programmable state, and to said alternate output when in a predetermined one of said first and second programmable states, includes a static architecture bit.

Claim 12

The macrocell of claim 1, wherein the register means includes a multiplexer for selecting between the output of the register and the output of the OR gate as an external output from the macrocell.

Claim 13

The macrocell of claim 1 wherein said means having two programmable states couples said product term to both said OR gate and said alternate output when in said first programmable state, and to said register means when in said second programmable state.

Claim 14

The macrocell of claim 1 wherein said means having two programmable states couples said product term to said OR gate when in said first programmable state, and to both said register means and said alternate output when in said second programmable state.

Claim 15

A programmable logic device comprising: a first macrocell having an OR gate for summing product terms, a register means and means for receiving a product term; a second macrocell having an OR gate for summing product terms; a first static architecture bit having first and second programmable states; a second static architecture bit having first and second programmable states; means for coupling the output of the OR gate of the first macrocell to an input of the OR gate of the second macrocell when the first static architecture bit is in its first programmable state and for coupling the output of the OR gate of the first macrocell to an input to the register means of the first macrocell when the first static architecture bit is in its second programmable state; and means for coupling the product term to the OR gate of the first macrocell when the second static architecture bit is in its first programmable state and to the register means of the first macrocell when the second static architecture bit is in its second programmable state, and for additionally coupling said product term to an alternate output when said second static architecture bit is in a predetermined one of said first and second programmable states, said alternate output thereby functioning as an expander.

Claim 16

A programmable logic device comprising: a first macrocell having an OR gate for summing product terms, a register means and means for receiving a product term; a second macrocell having an OR gate for summing product terms; a first static architecture bit having first and second programmable states; a second static architecture bit having first and second programmable states; means for coupling the output of the OR gate of the first macrocell to an input of the OR gate of the second macrocell when the first static architecture bit is in its first programmable state and for coupling the output of the OR gate of the first macrocell to an input to the register means of the first macrocell when the first static architecture bit is in its second programmable state; and means for coupling the product term to the OR gate of the first macrocell when the second static architecture bit is in its first programmable state and to the register means of the first macrocell when the second static architecture bit is in its second programmable state, and for additionally coupling said product term to an alternate output when said second static architecture bit is in a predetermined one of said first and second programmable states, said alternate output thereby functioning as an expander.

Claim 17

The programmable logic device of claim 14 wherein said means for coupling the product term couples said product term to both said OR gate of the first macrocell and to said alternate output when said second static architecture bit is in said first programmable state, and to said register means of the first macrocell when said second static architecture bit is in said second programmable state.

Claim 18

The programmable logic device of claim 14 wherein said means for coupling said product term couples said product term to said OR gate of the first macrocell when said second static architecture bit is in said first programmable state, and to both said register means of the first macrocell and said alternate output when said second static architecture bit is in said second programmable state.