High-performance programmable logic device

Claim 2

A programmable logic device comprising a programmable AND gate array having inputs for receiving input signals and generating a plurality of product terms, a programmable OR gate array connected to receive product terms from said AND gate array and producing sum terms of products, said individual sum terms from said OR gate array serving multiple functions based upon programming of said macrocell, a plurality of programmable macrocells each connected to receive a plurality of said sum terms from said programmable OR gate array, each macrocell including a first programmable register means for receiving sum terms, an I/O terminal means connected to receive outputs from said programmable register means, a first feedback from said register means to said AND gate array.

Claim 3

The programmable logic device as defined by claim 1 and further including clock circuit means for said register means responsive to an external clock or a sum term.

Claim 4

The device as defined by claim 1 wherein said plurality of macrocells is organized into two cell groups, each cell group responding to group control signals including group preload, group unload, and group clock.

Claim 5

The programmable logic device as defined by claim 1 wherein said programmable register means is configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop.

Claim 6

The programmable logic device as defined by claim 4 wherein said programmable register means is dynamically alterable for individually controlled macrocells.

Claim 7

A programmable logic device comprising a programmable AND gate aarray having inputs for receiving input signals and generating a plurality of product terms, a programmable OR gate array connected to receive product terms from said AND gate array and producing sum terms of products, individual sum terms from said OR gate array serve multiple functions based upon programming of said macrocell, a first sum term is used as an input to a flip-flop, a second sum term is used as a preset signal and as an input to a flip-flop, a third sum term is used as a reset signal and as a clock signal, and a fourth sum term is used as an output-enable and as a clock signal, a plurality of programmable macrocells each connected to receive a plurality of said sum terms from said programmable OR gate array each macrocell including a first programmable register means for receiving sum terms and configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, said programmable register means is dynamically alterable for individually controlled macrocells, an I/O terminal means connected to receive outputs from said programmable register means, a first feedback from said register means to said AND gate array, a second feedback from said I/O terminal to said AND gate array wherein said register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functions combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said AND gate array or as an output to an I/O terminal, and clock circuit means for said register means responsive to an external clock or a sum term.

Claim 8

A programmable logic device comprising a programmable AND gate aarray having inputs for receiving input signals and generating a plurality of product terms, a programmable OR gate array connected to receive product terms from said AND gate array and producing sum terms of products, individual sum terms from said OR gate array serve multiple functions based upon programming of said macrocell, a first sum term is used as an input to a flip-flop, a second sum term is used as a preset signal and as an input to a flip-flop, a third sum term is used as a reset signal and as a clock signal, and a fourth sum term is used as an output-enable and as a clock signal, a plurality of programmable macrocells each connected to receive a plurality of said sum terms from said programmable OR gate array each macrocell including a first programmable register means for receiving sum terms and configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, said programmable register means is dynamically alterable for individually controlled macrocells, an I/O terminal means connected to receive outputs from said programmable register means, a first feedback from said register means to said AND gate array, a second feedback from said I/O terminal to said AND gate array wherein said register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functions combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said AND gate array or as an output to an I/O terminal, and clock circuit means for said register means responsive to an external clock or a sum term.

Claim 9

The programmable logic device as defined by claim 6 and further including second register means connected to said I/O terminal means and wherein said I/O terminal means is responsive to an output-enable control signal to function as a latched input to said AND gate array, a register input to said AND gate array, a dedicated output, and as an I/O terminal with no register or latch.

Claim 10

The programmable logic device as defined by claim 7 and further including means for preloading and unloading said programmable register means.

Claim 11

A programmable logic device comprising a programmable AND gate array having inputs for receiving input signals and generating a plurality of product terms, a programmable OR gate array connected to receive product terms from said AND gate array and producing sum terms of products, said programmable register means being configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, and wherein a first sum term is operable as an input to a flip-flop, a second term is operable as a preset signal and as an input to a flip-flop, a third sum term is operable as a reset signal and as a clock signal, and a fourth sum term is operable as an output-enable and as a clock signal, a plurality of programmable macrocells each connected to receive a plurality of said sum terms from said programmable OR gate array each macrocell including a first programmable register means for receiving sum terms, an I/O terminal means connected to receive outputs from said programmable register means, a first feedback from said register means to said AND gate array, a second feedback from said I/O terminal to said AND gate array wherein said register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functions combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said AND gate array or as an output to an I/O terminal, and clock circuit means responsive to an external clock and to a sum term.

Claim 12

A programmable logic device comprising a programmable AND gate array having inputs for receiving input signals and generating a plurality of product terms, a programmable OR gate array connected to receive product terms from said AND gate array and producing sum terms of products, said programmable register means being configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, and wherein a first sum term is operable as an input to a flip-flop, a second term is operable as a preset signal and as an input to a flip-flop, a third sum term is operable as a reset signal and as a clock signal, and a fourth sum term is operable as an output-enable and as a clock signal, a plurality of programmable macrocells each connected to receive a plurality of said sum terms from said programmable OR gate array each macrocell including a first programmable register means for receiving sum terms, an I/O terminal means connected to receive outputs from said programmable register means, a first feedback from said register means to said AND gate array, a second feedback from said I/O terminal to said AND gate array wherein said register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functions combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said AND gate array or as an output to an I/O terminal, and clock circuit means responsive to an external clock and to a sum term.

Claim 13

The programmable logic device as defined by claim 9 and further including second register means connected with said I/O terminal means and wherein said I/O terminal means is responsive to an output-enable control signal to function as a latched input to said AND gate array, a registered input to said AND gate array, a dedicated output, and an I/O terminal with no register or latch.

Claim 14

For use in a programmable logic device in which a gate array produces product sum terms, a macrocell comprising a programmable register means for receiving a plurality of sum terms, an I/O terminal means connected to receive an output from said programmable register means and connected to receive sum terms, a first feedback from said register means to said gate array, and a second feedback from said I/O terminal means to said gate array wherein said programmable register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functional combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said gate array or as an output to an I/O terminal, and sum terms from the gate array serve multiple functions based on programming of said macrocell.

Claim 15

For use in a programmable logic device in which a gate array produces product sum terms, a macrocell comprising a programmable register means for receiving a plurality of sum terms, an I/O terminal means connected to receive an output from said programmable register means and connected to receive sum terms, a first feedback from said register means to said gate array, and a second feedback from said I/O terminal means to said gate array wherein said programmable register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functional combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said gate array or as an output to an I/O terminal, and sum terms from the gate array serve multiple functions based on programming of said macrocell.

Claim 16

The macrocell as defined by claim 11 wherein said programmable register means is configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop.

Claim 17

The macrocell as defined by claim 12 wherein said programmable register means is dynamically alterable for individually controlled macrocells.

Claim 18

For use in a programmable logic device in which a gate array produces product sum terms, a macrocell comprising programmable register means for receiving a plurality of sum terms, said programmable register means being configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, said programmable register means being dynamically alterable for individually controlled macrocells and serving multiple functions based on programming of said macrocell, a first sum term is used as an input to a flip-flop, a second sum term is used as a preset signal and as an input to a flip-flop, a third sum term is used as a reset signal and as a clock signal, and a further sum term is used as an output-enable and as a clock signal, an I/O terminal means connected to receive an output from said programmable register means and connected to receive sum terms, a first feedback from said register means to said gate array, and a second feedback from said I/O terminal means to said gate array wherein said programmable register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functional combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said gate array or as an output to an I/O terminal.

Claim 19

For use in a programmable logic device in which a gate array produces product sum terms, a macrocell comprising programmable register means for receiving a plurality of sum terms, said programmable register means being configurable as either a D flip-flop, a T flip-flop, or a JK flip-flop, said programmable register means being dynamically alterable for individually controlled macrocells and serving multiple functions based on programming of said macrocell, a first sum term is used as an input to a flip-flop, a second sum term is used as a preset signal and as an input to a flip-flop, a third sum term is used as a reset signal and as a clock signal, and a further sum term is used as an output-enable and as a clock signal, an I/O terminal means connected to receive an output from said programmable register means and connected to receive sum terms, a first feedback from said register means to said gate array, and a second feedback from said I/O terminal means to said gate array wherein said programmable register means and said I/O terminal means can function independently, each macrocell being functional in simultaneously implementing two independent sum-of-product logic functional combinatorially and sequentially with each of said logic functions being programmably routed as feedback signals to said gate array or as an output to an I/O terminal.

Claim 20

The macrocell as defined by claim 14 and further including a second register means connected to said I/O terminal means and wherein said I/O terminal means is responsive to an output-enable control signal to function as a latched input to said gate array, a registered input to said gate array, a dedicated output, and an I/O terminal with no register or latch.

Claim 21

The macrocell as defined by claim 15 and further including means for preloading and unloading said programmable register means.

Claim 22

The macrocell as defined in claim 14 and further including clock circuit means for said register means responsive to an external clock for to a sum term.

Claim 23

The macrocell as defined by claim 17 and further including means for inverting the polarity of clock pulses.