US5121006A
Expired / Lapsed
US
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Registered logic macrocell with product term allocation and adjacent product term stealing
Assignee: Altera Corp
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Filing: 1991-04-22
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Granted: 1992-06-09
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Expires: 2011-04-22
Abstract
Abstract A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.
Inventors
- 👤 Bruce B. Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
88 words
A macrocell comprising: an OR gate; means for coupling an external signal to a first input to the OR gate; a register means; means for receiving a product term; means having two programmable states for coupling the product term (a) to a second input to the OR gate when in a first programmable state and (b) to the register means when in a second programmable state; and means for programmably coupling the output of the OR gate to the input to an OR gate in a second macrocell.
Claim 2
Dependent Claim
88 words
A macrocell comprising: an OR gate; means for coupling an external signal to a first input to the OR gate; a register means; means for receiving a product term; means having two programmable states for coupling the product term (a) to a second input to the OR gate when in a first programmable state and (b) to the register means when in a second programmable state; and means for programmably coupling the output of the OR gate to the input to an OR gate in a second macrocell.
Claim 3
Dependent Claim
13 words
The macrocell of claim 1, wherein the register means includes a D flip-flop.
Claim 4
Dependent Claim
13 words
The macrocell of claim 1, wherein the register means includes a T flip-flop.
Claim 5
Dependent Claim
106 words
The macrocell of claim 1, wherein the register means includes: a first multiplexer having a product term as a first input and a sum of product terms as a second input; a second multiplexer having a product term as a first input, a static LOW as a second input, the output of the register as a third input, and the inverted output of the register as a fourth input; and an EXCLUSIVE-OR gate having a first input from the output of said first multiplexer and a second input from the output of said second multiplexer, and having its output coupled to the input to the register.
Claim 6
Dependent Claim
31 words
The macrocell of claim 1, wherein the register means includes a multiplexer for selecting between a product term or an external clock signal for driving a clock input to the register.
Claim 7
Dependent Claim
19 words
The macrocell of claim 1, wherein the means includes means for using a product term to enable the register.
Claim 8
Dependent Claim
20 words
The macrocell of claim 1, wherein the register means includes means for using a product term for presetting the register.
Claim 9
Dependent Claim
20 words
The macrocell of claim 1, wherein the register means includes means for using a product term to clear the register.
Claim 10
Dependent Claim
33 words
The macrocell of claim 1, wherein the means for programmably coupling the output of the OR gate to the input to an OR gate in a second macrocell includes a static architecture bit.
Claim 11
Dependent Claim
49 words
The macrocell of claim 1, wherein the means having two programmable states for coupling the product term (a) to a second input to the OR gate when in a first programmable state and (b) to the register means when in a second programmable state, includes a static architecture bit.
Claim 12
Dependent Claim
34 words
The macrocell of claim 1, wherein the register means includes a multiplexer for selecting between the output of the register and the output of the OR gate as an external output from the macrocell.
Claim 13
Dependent Claim
183 words
A programmable logic device comprising: a first macrocell having an OR gate for summing product terms, a register means and means for receiving a product term; a second macrocell having an OR gate for summing product terms; a first static architecture bit having a first and a second programmable states; a second static architecture bit having a first and a second programmable states; means for coupling the output of the OR gate of the first macrocell to an input of the OR gate of the second macrocell when the first static architecture bit is in its first programmable state and for coupling the output of the OR gate of the first macrocell to an input to the register means of the first macrocell when the first static architecture bit is in its second programmable state; and means for coupling the product term to the OR gate of the first macrocell when the second static architecture bit is in its first programmable state and to the register means of the first macrocell when the second static architecture bit is in its second programmable state.
Claim 14
Dependent Claim
183 words
A programmable logic device comprising: a first macrocell having an OR gate for summing product terms, a register means and means for receiving a product term; a second macrocell having an OR gate for summing product terms; a first static architecture bit having a first and a second programmable states; a second static architecture bit having a first and a second programmable states; means for coupling the output of the OR gate of the first macrocell to an input of the OR gate of the second macrocell when the first static architecture bit is in its first programmable state and for coupling the output of the OR gate of the first macrocell to an input to the register means of the first macrocell when the first static architecture bit is in its second programmable state; and means for coupling the product term to the OR gate of the first macrocell when the second static architecture bit is in its first programmable state and to the register means of the first macrocell when the second static architecture bit is in its second programmable state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-09 | 1995-12-09 | 1996-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-09 | 1999-12-09 | 2000-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-09 | 2003-12-09 | 2004-06-09 | $7700.00 | Window Closed / Lapsed |