Logic cell for programmable logic devices

Claim 2

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein each of said modules further includes circuitry for selectively disabling the register of said module in response to a disable-type signal, wherein said programmable logic array integrated circuit further comprises a plurality of sources of potential disable-control signals, and wherein said signal selection circuitry additionally derives said disable-type signal to be used by all of said modules in the associated region by selecting among said potential disable-control signals.

Claim 3

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein each of said modules further includes circuitry for selectively applying said intermediate signal of said module to said register of said module for registering by said register in response to application of a normal-type signal, wherein said programmable logic array integrated circuit further comprises a plurality of sources of potential normal-control signals, and wherein said signal selection circuitry additionally derives said normal-type signal to be used by all of said modules in the associated region by selecting among said potential normal-control signals.

Claim 4

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein each of said modules further includes circuitry for selectively applying said intermediate signal of said module to said register of said module for registering by said register in response to application of a normal-type signal, wherein said programmable logic array integrated circuit further comprises a plurality of sources of potential normal-control signals, and wherein said signal selection circuitry additionally derives said normal-type signal to be used by all of said modules in the associated region by selecting among said potential normal-control signals.

Claim 5

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein each of said modules further includes circuitry for selectively applying an input signal of said module to said register for registering by said register in response to application of a load-type signal, wherein said programmable logic array integrated circuit further comprises a plurality of sources of potential load-control signals, and wherein said signal selection circuitry additionally derives said load-type signal to be used by all of said modules in the associated region by selecting among said potential load-control signals.

Claim 6

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein each of said modules further includes circuitry for selectively applying an input signal of said module to said register for registering by said register in response to application of a load-type signal, wherein said programmable logic array integrated circuit further comprises a plurality of sources of potential load-control signals, and wherein said signal selection circuitry additionally derives said load-type signal to be used by all of said modules in the associated region by selecting among said potential load-control signals.

Claim 7

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein in addition to said inputs each of said modules receives a carry in signal, wherein in addition to said intermediate output each of said modules produces a carry out signal which is the carry in signal to another module, wherein each of said modules includes carry selection circuitry for selectively substituting for one of the inputs of the module the carry in signal received by that module in response to application of a carry select signal, and wherein said programmable logic array integrated circuit further comprises: a programmable carry select function control element associated with each of said regions for selectively applying a common carry select signal to all of the modules in said region.

Claim 8

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein in addition to said inputs each of said modules receives a carry in signal, wherein in addition to said intermediate output each of said modules produces a carry out signal which is the carry in signal to another module, wherein each of said modules includes carry selection circuitry for selectively substituting for one of the inputs of the module the carry in signal received by that module in response to application of a carry select signal, and wherein said programmable logic array integrated circuit further comprises: a programmable carry select function control element associated with each of said regions for selectively applying a common carry select signal to all of the modules in said region.

Claim 9

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein said register in each of said modules comprises: first and second flow-through latch circuits connected in series and having respective first and second input gating transistors, said first and second input gating transistors being controlled by respective first and second clock-type signals applied by said signal selection circuitry associated with the region that includes the module, said signal selection circuitry being capable of producing said first and second clock-type signals independently of one another so that said first clock-type signal can either be (1) a phase-shifted version of said second clock-type signal so that said register operates as a flip-flop, or (2) held constant while said second clock-type signal continues to be cyclic so that said register operates as a flow-through latch.

Claim 10

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register requiring the application of a clock-type signal in order to register said associated signal; a plurality of sources of potential clock-type signals; programmable function control elements associated with each of said regions; and signal selection circuitry associated with each of said regions and responsive to the function control elements associated with said region for selecting said clock-type signal to be used by all of said modules in the associated region from among said plurality of potential clock-type signals; wherein said register in each of said modules comprises: first and second flow-through latch circuits connected in series and having respective first and second input gating transistors, said first and second input gating transistors being controlled by respective first and second clock-type signals applied by said signal selection circuitry associated with the region that includes the module, said signal selection circuitry being capable of producing said first and second clock-type signals independently of one another so that said first clock-type signal can either be (1) a phase-shifted version of said second clock-type signal so that said register operates as a flip-flop, or (2) held constant while said second clock-type signal continues to be cyclic so that said register operates as a flow-through latch.

Claim 11

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register having a function which is controlled by a register-control signal applied to said register; a programmable counter selection function control element associated with each of said regions for selectively indicating that the modules in the region are to be used to provide respective stages of a counter; and signal selection circuitry associated with each of said regions and responsive to the counter selection function control element of the region for selecting one of said input signals of one of the modules in the region as a source for the register-control signal applied to the registers of all of the modules in the region.

Claim 12

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of said regions including a plurality of modules of programmable logic, each of said modules including programmable logic circuitry for producing an intermediate signal which is any of a plurality of logical functions of a plurality of input signals applied to the module and a register for selectively registering a signal associated with the module, said register having a function which is controlled by a register-control signal applied to said register; a programmable counter selection function control element associated with each of said regions for selectively indicating that the modules in the region are to be used to provide respective stages of a counter; and signal selection circuitry associated with each of said regions and responsive to the counter selection function control element of the region for selecting one of said input signals of one of the modules in the region as a source for the register-control signal applied to the registers of all of the modules in the region.

Claim 13

The apparatus defined in claim 6 wherein the function controlled by said register-control signal is clearing the register.

Claim 14

The apparatus defined in claim 6 wherein the function controlled by said register-control signal is loading the register.

Claim 15

The apparatus defined in claim 6 wherein the function controlled by said register-control signal is enabling the register to respond to newly applied data.

Claim 16

The apparatus defined in claim 6 wherein the input signals of each module include a first input signal which can be data stored in the register of the module, a second input signal which can be one place of a count interval value, a third input signal which can be a carry in signal from a module performing a less significant place of counting, and a fourth input signal, and wherein said signal selection circuitry selects the fourth input signal of said one of said modules as said source.

Claim 17

The apparatus defined in claim 10 wherein the input signals of each module further include a fifth input signal, and wherein the function controlled by said register-control signal is loading the register with the fifth input signal.

Claim 18

A programmable logic array integrated circuit comprising: a plurality of modules of programmable logic, each of said modules being programmable to produce any of a plurality of logical functions of a plurality of input signals applied to the module to produce a main output signal and, depending on the logical function, a carry out signal, the input signals of each module including a carry in signal which is generally the carry out signal of a preceding module in a carry chain; and feedback circuitry associated with a predetermined one of said modules which can be a first module in a carry chain for applying the main output signal of said module to the carry in input of said module.

Claim 19

A programmable logic array integrated circuit comprising: a plurality of modules of programmable logic, each of said modules being programmable to produce any of a plurality of logical functions of a plurality of input signals applied to the module to produce a main output signal and, depending on the logical function, a carry out signal, the input signals of each module including a carry in signal which is generally the carry out signal of a preceding module in a carry chain; and feedback circuitry associated with a predetermined one of said modules which can be a first module in a carry chain for applying the main output signal of said module to the carry in input of said module.

Claim 20

The apparatus defined in claim 12 wherein said feedback circuitry comprises: a programmable selector for applying either the main output signal of said predetermined one of said modules or the carry out signal of another one of said modules to said carry in input of said predetermined one of said modules.