US5218240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic cell and array with bus repeaters
Assignee: Atmel Corp
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Filing: 1992-08-25
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Granted: 1993-06-08
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Expires: 2012-08-25
Abstract
Abstract A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
Inventors
- 👤 Rafael C. Camarota
- 👤 Frederick C. Furtek
- 👤 Walford W. Ho
- 👤 Edward H. Browder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
99 words
In a two dimensional array of logic cells, each cell except those at the edges of the array having four nearest neighbors so as to form rows and columns of said cells, a bus network for transmitting signals within the array comprising: a local bus, a turning bus and an express bus provided for every row and column of the array formed by said cells, repeater means for driving said buses, said repeater means partitioning said buses of a given row or column so as to form bus segments, each bus segment spanning a plurality of said logic cells.
Claim 2
Dependent Claim
99 words
In a two dimensional array of logic cells, each cell except those at the edges of the array having four nearest neighbors so as to form rows and columns of said cells, a bus network for transmitting signals within the array comprising: a local bus, a turning bus and an express bus provided for every row and column of the array formed by said cells, repeater means for driving said buses, said repeater means partitioning said buses of a given row or column so as to form bus segments, each bus segment spanning a plurality of said logic cells.
Claim 3
Dependent Claim
31 words
The apparatus of claim 1 wherein the repeater means forming the bus segments are aligned in rows and columns which partition said array of cells into rectangular blocks of said cells.
Claim 4
Dependent Claim
34 words
The apparatus of claim 1 wherein each local bus segment is connected to every cell spanned by that bus segment so as to provide an electrical connection between the cells and the bus network.
Claim 5
Dependent Claim
31 words
The apparatus of claim 1 wherein each turning bus segment provides an electrical connection to all orthogonal bus segments between a row of the array and a column of the array.
Claim 6
Dependent Claim
23 words
The apparatus of claim 1 wherein the express bus segment is connected solely to the two repeater means forming said express bus segment.
Claim 7
Dependent Claim
45 words
The apparatus of claim 1 wherein the repeater means is programmable to connect any bus connected to one side of the repeater means to any bus connected to one side of the repeater means to any bus connected to the other side of the repeater.
Claim 8
Dependent Claim
17 words
The apparatus of claim 1 wherein the repeater means provides electrical signal regeneration for each programmable connection.
Claim 9
Dependent Claim
28 words
The apparatus of claim 1 wherein the repeater means is programmable so as to select the electrical signal direction through the repeater means for a given bus connection.
Claim 10
Dependent Claim
114 words
A programmable logic array comprising: a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest neighbors, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in which said cells are aligned in rows and columns, and clock distribution means for providing independent timing signals to said logic cells, said clock distribution means comprising one multiplexer for each column of the array, each multiplexer having a plurality of inputs and one output, said output being connected to each logic cell in the given column.
Claim 11
Dependent Claim
114 words
A programmable logic array comprising: a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest neighbors, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in which said cells are aligned in rows and columns, and clock distribution means for providing independent timing signals to said logic cells, said clock distribution means comprising one multiplexer for each column of the array, each multiplexer having a plurality of inputs and one output, said output being connected to each logic cell in the given column.
Claim 12
Dependent Claim
56 words
The apparatus of claim 9 wherein said multiplexer in the clock distribution means has four inputs, a first input to said multiplexer being a constant logical signal, said second input coming from an external timing source, said third input coming from an express bus and said fourth input coming from the output of a logic cell.
Claim 13
Dependent Claim
34 words
The apparatus of claim 9 wherein the timing signal provided to the logic cells of a given column of the array is independent from the timing signal of any other column of the array.
References Cited (Backward Citations)
US4642487A
Cited
US4786904A
Cited
US4812684A
Cited
US4918641A
Cited
US4855619A
Cited
US4912342A
Cited
US5073729A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |