US5623217A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field programmable gate array with write-port enabled memory
Assignee: Lattice Semiconductor Corp
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Filing: 1996-02-26
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Granted: 1997-04-22
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Expires: 2016-02-26
Abstract
Abstract A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.
Inventors
- 👤 Barry K. Britton
- 👤 Kai-Kit Ngai
- 👤 Satwant Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
83 words
An integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized in that said programmable function units each comprise a write-strobe input and a write-port enable input, wherein data may be written into said random access memory when both said write-strobe input and said write-port enable input are active.
Claim 2
Dependent Claim
83 words
An integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized in that said programmable function units each comprise a write-strobe input and a write-port enable input, wherein data may be written into said random access memory when both said write-strobe input and said write-port enable input are active.
Claim 3
Dependent Claim
48 words
The invention of claim 1 further comprising tri-state output buffers having their inputs connected to the random access memory data outputs of associated programmable function units, and each of said output buffers having a control input connected to the write-port enable input of the associated programmable function unit.
Claim 4
Dependent Claim
32 words
The invention of claim 1 further comprising an address decoder having inputs connected to higher-order address lines and having decoded outputs connected to said write-port enable inputs of said programmable function units.
Claim 5
Dependent Claim
37 words
The invention of claim 1 further comprising a clock input, wherein both the write-strobe input and the write-port enable input must be active during a clock edge in order to write data into the random access memory.
Claim 6
Dependent Claim
45 words
The invention of claim 1 wherein either the write-strobe input or the write-port enable input may be used for functions other than controlling the writing of data into said programmable function unit when said programmable function unit is not used as a random access memory.
Claim 7
Dependent Claim
155 words
An integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized in that said programmable function units each comprise a write-strobe input and a write-port enable input, wherein data may be written into said random access memory when both said write-strobe input and said write-port enable input are active, and further comprising tri-state output buffers having their inputs connected to the random access memory data outputs of associated programmable function units, and each of said output buffers having a control input connected to the write-port enable input of the associated programmable function unit, and further comprising an address decoder having inputs connected to higher-order address lines and having decoded outputs connected to said write-port enable inputs of said programmable function units.
Claim 8
Dependent Claim
155 words
An integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized in that said programmable function units each comprise a write-strobe input and a write-port enable input, wherein data may be written into said random access memory when both said write-strobe input and said write-port enable input are active, and further comprising tri-state output buffers having their inputs connected to the random access memory data outputs of associated programmable function units, and each of said output buffers having a control input connected to the write-port enable input of the associated programmable function unit, and further comprising an address decoder having inputs connected to higher-order address lines and having decoded outputs connected to said write-port enable inputs of said programmable function units.
Claim 9
Independent Claim
86 words
A method of programming an integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized by supplying to said programmable function units a write-strobe signal and a write-port enable signal, wherein data may be written into said random access memory when both said write-strobe signal and said write-port enable signal are provided.
Claim 10
Independent Claim
86 words
A method of programming an integrated circuit comprising a field programmable gate array comprising an array of programmable function units that each comprise an array of memory cells that can be user-configured as either a look-up table for performing logic functions, or alternatively as a random access memory, Characterized by supplying to said programmable function units a write-strobe signal and a write-port enable signal, wherein data may be written into said random access memory when both said write-strobe signal and said write-port enable signal are provided.
Claim 11
Dependent Claim
49 words
The invention of claim 7 further comprising providing tri-state output buffers having their inputs connected to the random access memory data outputs of associated programmable function units, and each of said output buffers having a control input connected to the write-port enable input of the associated programmable function unit.
Claim 12
Dependent Claim
33 words
The invention of claim 7 further comprising providing an address decoder having inputs connected to higher-order address lines and having decoded outputs connected to said write-port enable inputs of said programmable function units.
Claim 13
Dependent Claim
36 words
The invention of claim 7 further comprising providing a clock signal, whereby data is written into the random access memory when both the write-strobe signal and the write-port enable signal are provided during a clock edge.
Claim 14
Dependent Claim
44 words
The invention of claim 7 further comprising using either the write-strobe signal or the write-port enable signal for functions other than controlling the writing of data into said programmable function unit when said programmable function unit is not used as a random access memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-21 | 2000-10-21 | 2001-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-21 | 2004-10-21 | 2005-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-21 | 2008-10-21 | 2009-04-22 | $7700.00 | Window Closed / Lapsed |