US5488316A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for selecting a bit in a look-up table
Assignee: Xilinx Inc
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Filing: 1995-04-26
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Granted: 1996-01-30
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Expires: 2015-04-26
Abstract
Abstract This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.
Inventors
- 👤 Ross H. Freeman
- 👤 Hung-Cheng Hsieh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
182 words
A structure for selecting a bit in a look-up table including a first input line for receiving a first input signal and a second input line for receiving a second input signal, said structure comprising: a first inverter coupled to said first input line for providing the complement of said first input signal; a second inverter coupled to said first inverter for providing the logic state of said first input signal; a third inverter coupled to said second input line for providing the complement of said second input signal; and a fourth inverter coupled to said third inverter for providing the logic state of said second input signal; a first, second, third, and fourth logic gate, wherein said first inverter is coupled to said first and second logic gates, said second inverter is coupled to said third and fourth logic gates, said third inverter is coupled to said second and fourth logic gates, and said fourth inverter is coupled to said first and third logic gates, wherein each of said logic gates controls the transfer of a bit in said look-up table.
Claim 2
Dependent Claim
182 words
A structure for selecting a bit in a look-up table including a first input line for receiving a first input signal and a second input line for receiving a second input signal, said structure comprising: a first inverter coupled to said first input line for providing the complement of said first input signal; a second inverter coupled to said first inverter for providing the logic state of said first input signal; a third inverter coupled to said second input line for providing the complement of said second input signal; and a fourth inverter coupled to said third inverter for providing the logic state of said second input signal; a first, second, third, and fourth logic gate, wherein said first inverter is coupled to said first and second logic gates, said second inverter is coupled to said third and fourth logic gates, said third inverter is coupled to said second and fourth logic gates, and said fourth inverter is coupled to said first and third logic gates, wherein each of said logic gates controls the transfer of a bit in said look-up table.
Claim 3
Dependent Claim
17 words
The structure of claim 1 wherein said first, second, third, and fourth logic gates are NOR gates.
Claim 4
Dependent Claim
62 words
The structure of claim 1 further comprising: a first multiplexer connected to receive a first plurality of signals from an interconnect structure and having a first output line connected to said first input line; and a second multiplexer connected to receive a second plurality of signals from said interconnect structure and having a second output line connected to said second input line.
References Cited (Backward Citations)
US4422160A
Cited
US4791602A
Cited
US4990992A
Cited
US4896296A
Cited
US4670748A
Cited
US4796234A
Cited
US4845633A
Cited
JPS62238642A
Cited
US4791603A
Cited
US4873459B1
Cited
US4873459A
Cited
US4879684A
Cited
US4881200A
Cited
US4876466A
Cited
US5109353A
Cited
US5021689A
Cited
US4942319A
Cited
US4998223A
Cited
US5343406A
Cited
US5432719A
Cited
US5231588A
Cited
US4972105A
Cited
US4975601A
Cited
US5338981A
Cited
US5216636A
Cited
US5315178A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |