Patent US4953513A successfully refreshed from Google Patents.
US5216636A
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Cmos memory cell
Assignee: Advanced Micro Devices Inc
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Filing: 1991-09-16
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Granted: 1993-06-01
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Expires: 2011-09-16
Abstract
Abstract A dual port random access memory cell is coupled to complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line. The memory cell includes two two-transistor inverters (36, 38) cross-coupled to form a flip-flop core memory which is coupled to complementary input/output nodes (40, 42). A fifth transistor (44 or 56) has its main electrodes connected between the first input/output node (40) and the first read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). The sixth transistor (46 or 58) has its main electrodes connected between the second input/output node (42) and the second read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). A seventh transistor (48) has its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and has its gate electrode connected to the second input/output node (42). An eighth transistor (50 ) has its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and its gate electrode connected to the first input/output node (40). A ninth transistor (52) has its main electrodes connected between the common node (54) and the read-only date bit line (BLB) and its gate electrode connected to the read-only address line (ROW SELB).
Inventors
- 👤 Thomas J. Runaldue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/00; G11C7/12; G11C7/22; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
243 words
A dual port random access memory cell coupled to first and second complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line comprising: two two-transistor inverters (36, 38) cross-coupled to form a four transistor flip-flop core memory, said core memory being coupled to first and second complementary input/output nodes (40, 42); a fifth transistor (44 or 56) having its main electrodes connected between said first input/output node (40) and said first read/write data bit line (BLA) and having its gate electrode connected to sad read/write address line (ROW SELA or ROW SELA); a sixth transistor (46 or 58) having its main electrodes connected between said second input/output node (42) and said second read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a seventh transistor (48) having its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and having its gate electrode connected to said second input/output node (42); an eighth transistor (50) having its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and having its gate electrode connected to said first input/output node (40); and a ninth transistor (52) having its main electrodes connected between the common node (54) and said read-only data bit line (BLB) and having its gate electrode connected to said read-only address line (ROW SELB).
Claim 2
Dependent Claim
243 words
A dual port random access memory cell coupled to first and second complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line comprising: two two-transistor inverters (36, 38) cross-coupled to form a four transistor flip-flop core memory, said core memory being coupled to first and second complementary input/output nodes (40, 42); a fifth transistor (44 or 56) having its main electrodes connected between said first input/output node (40) and said first read/write data bit line (BLA) and having its gate electrode connected to sad read/write address line (ROW SELA or ROW SELA); a sixth transistor (46 or 58) having its main electrodes connected between said second input/output node (42) and said second read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a seventh transistor (48) having its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and having its gate electrode connected to said second input/output node (42); an eighth transistor (50) having its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and having its gate electrode connected to said first input/output node (40); and a ninth transistor (52) having its main electrodes connected between the common node (54) and said read-only data bit line (BLB) and having its gate electrode connected to said read-only address line (ROW SELB).
Claim 3
Dependent Claim
24 words
A dual port random access memory cell as claimed in claim 1, wherein said memory cell is implemented in complementary metal-oxide semiconductor (CMOS) technology.
Claim 4
Dependent Claim
30 words
A dual port random access memory cell as claimed in claim 2, wherein each of said two two-transistor inverters comprises a series P-conductivity type transistor and an N-conductivity type transistor.
Claim 5
Dependent Claim
25 words
A dual port random access memory cell as claimed in claim 3, wherein said fifth and sixth transistors are comprised of N-conductivity type transistors (44,46).
Claim 6
Dependent Claim
25 words
A dual port random access memory cell as claimed in claim 3, wherein said fifth and sixth transistors are comprised of P-conductivity type transistors (56,58).
Claim 7
Dependent Claim
24 words
A dual port random access memory cell as claimed in claim 4, wherein said seventh and eighth transistors are comprised of N-conductivity type transistors.
Claim 8
Dependent Claim
24 words
A dual port random access memory cell as claimed in claim 5, wherein said seventh and eighth transistors are comprised of N-conductivity type transistors.
Claim 9
Dependent Claim
23 words
A dual port random access memory cell as claimed in claim 6, wherein aid ninth transistor is comprised of and N-conductivity type transistor.
Claim 10
Dependent Claim
23 words
A dual port random access memory cell as claimed in claim 7, wherein said ninth transistor is comprised of an N-conductivity type transistor.
Claim 11
Dependent Claim
248 words
A dual port random access memory cell coupled to first and second complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line comprising: two two-transistor inverters (36, 38) cross-coupled to form a four transistor flip-flop core memory, said core memory being coupled to first and second complementary input/output nodes (40, 42); a first pass transistor (44 or 56) having its main electrodes connected between said first input/output node (40) and said first read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a second pass transistor (46 or 58) having its main electrodes connected between said second input/output node (42) and said second read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a first isolation transistor (48) having its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and having its gate electrode connected to said second input/output node (42); a second isolation transistor (50) having its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and having its gate electrode connected to said first input/output node (40); and a third pass transistor (52) having its main electrodes connected between the common node (54) and said read-only data bit line (BLB) and having its gate electrode connected to said read-only address line (ROW SELB).
Claim 12
Dependent Claim
248 words
A dual port random access memory cell coupled to first and second complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line comprising: two two-transistor inverters (36, 38) cross-coupled to form a four transistor flip-flop core memory, said core memory being coupled to first and second complementary input/output nodes (40, 42); a first pass transistor (44 or 56) having its main electrodes connected between said first input/output node (40) and said first read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a second pass transistor (46 or 58) having its main electrodes connected between said second input/output node (42) and said second read/write data bit line (BLA) and having its gate electrode connected to said read/write address line (ROW SELA or ROW SELA); a first isolation transistor (48) having its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and having its gate electrode connected to said second input/output node (42); a second isolation transistor (50) having its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and having its gate electrode connected to said first input/output node (40); and a third pass transistor (52) having its main electrodes connected between the common node (54) and said read-only data bit line (BLB) and having its gate electrode connected to said read-only address line (ROW SELB).
Claim 13
Dependent Claim
26 words
A dual port random access memory cell as claimed in claim 10, wherein said first and second pass transistors are comprised of N-conductivity type transistors (44,46).
Claim 14
Dependent Claim
26 words
A dual port random access memory cell as claimed in claim 10, wherein said first and second pass transistors are comprised of P-conductivity type transistors (56,58).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |