US4768172A
Expired / Lapsed
US
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Memory cell
Assignee: Toshiba Corp
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Filing: 1986-12-23
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Granted: 1988-08-30
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Expires: 2006-12-23
Abstract
Abstract A memory cell comprises a memory which memorizes binary information in a static manner, a first delivery device which gives the binary information to a first bit line based on the potential of a first word line, and a second delivery device which gives the binary information memorized in the memory to a second word line different from the first word line, without forming a current path between the memory and a second bit line different from the first bit line.
Inventors
- 👤 Tooru Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:51
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
96 words
A memory cell comprising: memory means for memorizing binary information in a static manner; first delivery means for giving the binary information to first and second bit lines respectively, based on potentials of first and second word lines; and second delivery means for giving the binary information memorized in said memory means to a third bit line different from the first and second bit lines, based on the potential of a third word line different from the first and second word lines, without forming a current path between said memory means and the third bit line.
Claim 2
Dependent Claim
96 words
A memory cell comprising: memory means for memorizing binary information in a static manner; first delivery means for giving the binary information to first and second bit lines respectively, based on potentials of first and second word lines; and second delivery means for giving the binary information memorized in said memory means to a third bit line different from the first and second bit lines, based on the potential of a third word line different from the first and second word lines, without forming a current path between said memory means and the third bit line.
Claim 3
Dependent Claim
29 words
The memory cell as claimed in claim 1 wherein said memory means is a bistable circuit equipped with an inverter circuit whose input-output terminals are connected to each other.
Claim 4
Dependent Claim
43 words
The memory cell as claimed in claim 1 wherein said first delivery means comprises a first P-channel MOS-type transistor, and said second delivery means comprises a second N-channel MOS-type transistor inverted between a ground and a bit line pre-charged to a high level.
Claim 5
Dependent Claim
45 words
The memory cell as claimed in claim 1 wherein said first delivery means comprises a first N-channel MOS transistor, and said second delivery means comprises a second P-channel MOS-type transistor inserted between a voltage source and a bit line pre-charged to a low level state.
Claim 6
Dependent Claim
18 words
The memory cell as claimed in claim 1 wherein said second delivery means comprises a clocked inverter circuit.
Claim 7
Dependent Claim
48 words
The memory cell as claimed in claim 3 wherein a bistable circuit as the memory means comprises two symmetric inverter circuits, each having input-output terminals, in which an input terminal of one of the inverter circuits is connected mutually to an output terminal of the other inverter circuit.
Claim 8
Dependent Claim
32 words
The memory cell as claimed in claim 6 wherein one of the input-output terminals of the inverter circuits is connected to a first N-channel MOS-type transistor that constitutes the first delivery means.
Claim 9
Dependent Claim
31 words
The memory cell as claimed in claim 7 wherein the other input-output terminal of the inverter circuits is connected to the second N-channel MOS-type transistor that constitutes the second delivery means.
Claim 10
Dependent Claim
57 words
The memory cell as claimed in claim 8 wherein the other input-output terminal of the inverter circuits is connected to the gate terminal of a second P-channel MOS-type transistor that constitutes the second delivery means, and the source-drain terminal of the second P-channel MOS-type transistor is connected to the source-drain terminal of the first P-channel MOS-type transistor.
Claim 11
Dependent Claim
37 words
The memory cell as claimed in claim 4 wherein one of an input-output terminals of an inverter circuit used in said memory means is connected to a first P-channel MOS-type transistor that constitutes the first delivery means.
Claim 12
Dependent Claim
25 words
The memory cell as claimed in claim 10 wherein the other input-output terminal of the inverter circuit is connected to the second P-channel MOS-type transistor.
Claim 13
Dependent Claim
57 words
The memory cell as claimed in claim 11 wherein the other input-output terminal of the inverter circuit is connected to the gate terminal of a second N-channel MOS-type transistor that constitutes the second delivery means, and the source-drain terminal of the second N-channel MOS-type transistor is connected to the source-drain terminal of the first N-channel MOS-type transistor.
Claim 14
Dependent Claim
35 words
The memory cell as claimed in claim 6 wherein one of the input-output terminals of the inverter circuits is connected to the input-output terminal of a clocked inverter circuit that constitutes the second delivery means.
References Cited (Backward Citations)
US4661928A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-30 | 1992-02-29 | 1992-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-30 | 1996-02-29 | 1996-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-30 | 2000-02-29 | 2000-08-30 | $7700.00 | Window Closed / Lapsed |