US4990992A
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1988-10-05
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Granted: 1991-02-05
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Expires: 2008-10-05
Abstract
Abstract A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wirings. Each circuit block is served with a signal via an aluminum layer. The signal supplied to the circuit block is transmitted to the circuit elements via an internal wiring. If the aluminum layer is broken the circuit block formed on the remote side beyond the broken portion fail to work properly. Therefore, breakage of the aluminum layer can be easily detected. Further, since signals are supplied to the circuit blocks via an aluminum layer, the memory array operates at increased speeds.
Inventors
- 👤 Makio Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B20/00; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/853; H10B12/30; H10B12/31; H10B20/20; H10P; H10P74/00; H10P74/20; H10P74/207; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
144 words
A semiconductor integrated circuit device comprising: a plurality of word lines extending in a first direction; a plurality of data lines extending in a second direction which is perpendicular to said first direction; first means for selecting a word line from said plurality of word lines and which applies a signal to the selected word line; a second means for selecting a pair of data lines from said plurality of data lines; sub-word lines extending in said first direction and being substantially parallel to said word lines, and at least two sub-word lines connected to each of said plurality of word lines; and each of said sub-lines being connected to a plurality of memory cells, each memory cell being connected to one of said data lines and the signal from said first means being supplied to said at least two sub-word lines substantially simultaneously.
Claim 2
Dependent Claim
144 words
A semiconductor integrated circuit device comprising: a plurality of word lines extending in a first direction; a plurality of data lines extending in a second direction which is perpendicular to said first direction; first means for selecting a word line from said plurality of word lines and which applies a signal to the selected word line; a second means for selecting a pair of data lines from said plurality of data lines; sub-word lines extending in said first direction and being substantially parallel to said word lines, and at least two sub-word lines connected to each of said plurality of word lines; and each of said sub-lines being connected to a plurality of memory cells, each memory cell being connected to one of said data lines and the signal from said first means being supplied to said at least two sub-word lines substantially simultaneously.
Claim 3
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 1, wherein each of said memory cells includes a MISFET with a gate electrode and source and drain regions.
Claim 4
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 2, wherein said gate electrode is connected to one of said sub-word lines and one of said source and drain regions is connected to one of said data lines.
Claim 5
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 3, wherein said gate electrode is integrally formed with one of said sub-word lines.
Claim 6
Dependent Claim
17 words
A semiconductor integrated circuit device according to claim 4, wherein said word lines are formed of aluminum.
Claim 7
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 5, wherein said sub-word comprise electrically conductive polycrysalline silicon layers.
Claim 8
Dependent Claim
16 words
A semiconductor integrated circuit device according to claim 1, wherein said first means is X-address decoder.
Claim 9
Dependent Claim
16 words
A semiconductor integrated circuit device according to claim 7, wherein said second means is Y-address decoder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-04 | 1994-08-06 | 1995-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-04 | 1998-08-06 | 1999-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-04 | 2002-08-06 | 2003-02-05 | $7700.00 | Window Closed / Lapsed |