Semiconductor memory

Claim 2

A semiconductor circuit comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a plurality of wiring leads formed of a conductive layer which are arranged so as to intersect said plurality of data lines, wherein said wiring leads operate as power source line or signal lines of signals for controlling operation timings of said semiconductor circuit, wherein said plurality of data lines are divided into a plurality of sub data lines in a lengthwise direction thereof, said semiconductor circuit further comprising: a plurality of said common lines each of which is disposed in common for at least two of said sub data lines and is connected to these sub data lines through a third switch; and control lines which transmit select signals generated by said column decoder, to the third switches in order to drive said third switches and are disposed in parallel with said sub data lines.

Claim 3

A semiconductor circuit according to claim 1, further comprising a plurality of sense amplifiers each of which differentially amplifies signals of two of said data lines which are arranged in parallel so as to be capacitively coupled with said wiring leads equally.

Claim 4

A semiconductor circuit according to claim 2, wherein asid memory cell is arranged at only one of two intersection points between said word line and said two data lines which have signals to be differentially amplified.

Claim 5

A semiconductor circuit according to claim 3, further comprising a circuit which precharges said two data lines to a voltage of a substantially intermediate level of two sorts of voltages to be written into said memory cell, said precharging being done before said word line is driven.

Claim 6

A semiconductor circuit according to claim 4, further comprising an active restore circuit which is disposed between two data line pairs to be differentially amplified and which is connected with said two data line pairs through first and second switches operating selectively, to charge the data line on a high potential side of that of said two data line pairs amplified by said sense amplifier.

Claim 7

A semiconductor circuit according to claim 2, wherein said sense amplifier has two data line pairs to be differentially amplified, on both its sides, and further wherein said sense amplifier is connected with said two data line pairs through first and second switches operating selectively.

Claim 8

A semiconductor circuit according to claim 5, further comprising common lines which are disposed between said two data line pairs and which are selectively connected to said two data line pairs by said first and second switches.

Claim 9

A semiconductor circuit according to claim 1, wherein said sub data lines and said control lines are formed of a first layer of aluminum, said wiring leads are formed of a second layer of aluminum, and said word lines are formed of a material which can be used in a self-alignment process.

Claim 10

A semiconductor circuit according to claim 1, wherein said control lines and said wiring leads are formed of a first layer of aluminum, said sub data lines are formed of a second layer of aluminum, and said word lines are formed of a material which can be used in a self-alignment process, and further wherein those of said third switches which are connected to a plurality of sub data lines most remote from said column decoder are disposed on the column decoder sides of said sub data lines, and said wiring leads are arranged so as to intersect the most remote sub data lines.

Claim 11

A semiconductor circuit according to claim 1, wherein said plurality of word lines are divided into sub word lines in a lengthwise direction thereof, and said row decoder has the divided sub word lines on upper and lower sides thereof and includes means to selectively drive the sub word lines on one of the upper and lower sides.

Claim 12

A semiconductor circuit comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a plurality of wiring leads formed of a conductive layer which are arranged so as to intersect said plurality of data lines, wherein said wiring leads operate as a power source line or signal lines of signals for controlling operation timings of said semiconductor circuit, wherein said plurality of data lines are divided into sub data lines in a lengthwise direction thereof, and said column decoder has said sub data lines on right and left sides thereof, said semiconductor circuit further comprising: a plurality of said common lines which are disposed in common for at least two of said sub data lines and which are connnected to these sub data lines through third switches; and control lines which transmit select signals generated by said column decoder to said third switches in order to drive them, which are respectively disposed in parallel with said sub data lines on the right and left sides of said column decoder and which are formed of the same conductor layer as that of said wiring leads, wherein those of said third switches which are connected to two sets of subdata lines most remote from the right and left sides of said column decoder respectively are disposed on the column decoder side of said sub data lines, and further wherein said wiring leads are arranged so as to intersect said two sets of sub data lines most remote from the right and left sides of said column decoder, respectively.

Claim 13

A semiconductor circuit comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a plurality of wiring leads formed of a conductive layer which are arranged so as to intersect said plurality of data lines, wherein said wiring leads operate as a power source line or signal lines of signals for controlling operation timings of said semiconductor circuit, wherein said plurality of data lines are divided into sub data lines in a lengthwise direction thereof, and said column decoder has said sub data lines on right and left sides thereof, said semiconductor circuit further comprising: a plurality of said common lines which are disposed in common for at least two of said sub data lines and which are connnected to these sub data lines through third switches; and control lines which transmit select signals generated by said column decoder to said third switches in order to drive them, which are respectively disposed in parallel with said sub data lines on the right and left sides of said column decoder and which are formed of the same conductor layer as that of said wiring leads, wherein those of said third switches which are connected to two sets of subdata lines most remote from the right and left sides of said column decoder respectively are disposed on the column decoder side of said sub data lines, and further wherein said wiring leads are arranged so as to intersect said two sets of sub data lines most remote from the right and left sides of said column decoder, respectively.

Claim 14

A semiconductor circuit comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a plurality of wiring leads formed of a conductive layer which are arranged so as to intersect said plurality of data lines, wherein said wiring leads operate as a power source line or signal lines of signals for controlling operation timings of said semiconductor circuit, wherein said row decoder and said column decoder are arranged in parallel with each other, and drive signals for fourth switches which connect said plurality of data lines and said common lines are transmitted from said column decoder by control lines which are formed of the same conductor layer as that of said wiring leads and which pass within a region where said data lines and said word lines exist.

Claim 15

A semiconductor circuit comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a plurality of wiring leads formed of a conductive layer which are arranged so as to intersect said plurality of data lines, wherein said wiring leads operate as a power source line or signal lines of signals for controlling operation timings of said semiconductor circuit, wherein said row decoder and said column decoder are arranged in parallel with each other, and drive signals for fourth switches which connect said plurality of data lines and said common lines are transmitted from said column decoder by control lines which are formed of the same conductor layer as that of said wiring leads and which pass within a region where said data lines and said word lines exist.

Claim 16

A semiconductor circuit according to claim 12, wherein said column decoder and said row decoder are arranged in proximity to each other.

Claim 17

A semiconductor memory according to claim 12, further comprising a circuit which clamps said control lines when they are not selected.

Claim 18

A semiconductor circuit according to claim 1, wherein said memory cell is composed of a transistor whose control terminal is connected to the word line, and a capacitance portion whose connection with the data line is controlled by said transistor.

Claim 19

A semiconductor circuit according to claim 1, wherein said row decoder and said column decoder include drivers for driving the word lines and the data lines respectively.

Claim 20

A memory device comprising: a memory array having a plurality of sub-arrays each of which comprises: a plurality of word lines; a plurality of sub data lines which are arranged in a direction intersecting said plurality of word lines, and a plurality of memory cells which are disposed at points of intersection between said plurality of word lines and said plurality of sub data lines; a plurality of common lines each of which is arranged in common to at least two of said sub data lines and which is connected to said sub data lines through first switching means; a plurality of control lines each of which is connected in common to at least two of said first switching means; a first decoder for selecting at least one of said plurality of word lines; and a second decoder for selecting one of said plurality of control lines, wherein said second decoder is arranged on one side of said memory array, wherein two of said plurality of sub data lines in each sub array form a pair of lines having complementary signals, wherein each of said memory cells includes a capacitance for storing a signal, and a transistor for connecting between said capacitance and the corresponding sub data line, and wherein said pair lines are respectively arranged in proximity to each other and in parallel with each other, said memory device further comprising a plurality of differential amplifiers for detecting a pair of memory signals on said pair lines.

Claim 21

A memory device comprising: a memory array having a plurality of sub-arrays each of which comprises: a plurality of word lines; a plurality of sub data lines which are arranged in a direction intersecting said plurality of word lines, and a plurality of memory cells which are disposed at points of intersection between said plurality of word lines and said plurality of sub data lines; a plurality of common lines each of which is arranged in common to at least two of said sub data lines and which is connected to said sub data lines through first switching means; a plurality of control lines each of which is connected in common to at least two of said first switching means; a first decoder for selecting at least one of said plurality of word lines; and a second decoder for selecting one of said plurality of control lines, wherein said second decoder is arranged on one side of said memory array, wherein two of said plurality of sub data lines in each sub array form a pair of lines having complementary signals, wherein each of said memory cells includes a capacitance for storing a signal, and a transistor for connecting between said capacitance and the corresponding sub data line, and wherein said pair lines are respectively arranged in proximity to each other and in parallel with each other, said memory device further comprising a plurality of differential amplifiers for detecting a pair of memory signals on said pair lines.

Claim 22

A memory device according to claim 17, wherein said plural control lines are arranged in parallel with said plural data lines, and said pair lines intersect each other midway.

Claim 23

A memory device according to claim 17, wherein the longitudinal directions of said first and second decoders are parallel with each other.

Claim 24

A memory device comprising: a memory array having a plurality of sub-arrays each of which comprises: a plurality of word lines; a plurality of sub data lines which are arranged in a direction intersecting said plurality of word lines, and a plurality of memory cells which are disposed at points of intersection between said plurality of word lines and said plurality of sub data lines; a plurality of common lines each of which is arranged in common to at least two of said sub data lines and which is connected to said sub data lines through first switching means; a plurality of control lines each of which is connected in common to at least two of said first switching means; a first decoder for selecting at least one of said plurality of word lines; and a second decoder for selecting one of said plurality of control lines, wherein said second decoder is arranged on one side of said memory array, wherein two of said plurality of sub data lines in each sub array form a pair of lines having complementary siganls, wherein each of said memory cells includes a flip-flop circuit and second switching means for connecting the input-output terminals of said flip-flop to said pair lines, respectively.

Claim 25

A memory device comprising: a memory array having a plurality of sub-arrays each of which comprises: a plurality of word lines; a plurality of sub data lines which are arranged in a direction intersecting said plurality of word lines, and a plurality of memory cells which are disposed at points of intersection between said plurality of word lines and said plurality of sub data lines; a plurality of common lines each of which is arranged in common to at least two of said sub data lines and which is connected to said sub data lines through first switching means; a plurality of control lines each of which is connected in common to at least two of said first switching means; a first decoder for selecting at least one of said plurality of word lines; and a second decoder for selecting one of said plurality of control lines, wherein said second decoder is arranged on one side of said memory array, wherein two of said plurality of sub data lines in each sub array form a pair of lines having complementary siganls, wherein each of said memory cells includes a flip-flop circuit and second switching means for connecting the input-output terminals of said flip-flop to said pair lines, respectively.

Claim 26

A memory device according to claim 20, wherein the longitudinal directions of said first and second decoders are parallel with each other.

Claim 27

A memory device according to claim 20, wherein said plural control lines are arranged in parallel with said plural data lines, and said pair lines intersect each other midway.

Claim 28

A memroy device according to claim 20, wherein each of said memory cells includes a capacitance for storing a signal, and a transistor for connecting between said capacitance and the corresponding data line, and wherein said pair lines are respectively arranged in proximity to each other and in parallel with each other, said memory device further comprising a plurality of differential amplifiers for detecting a pair of memory signals on said pair lines.

Claim 29

A semiconductor circuit according to claim 21, wherein said plurality of data lines are divided into a plurality of sub data lines in a lengthwise direction thereof, said semiconductor circuit further comprising: a plurality of said common lines each of which is disposed in common for at least two of said sub data lines and is connected to these sub data lines through a third switch; and control lines which transmit select signals generated by said column decoder, to the first switches in order to drive said third switches and are disposed in parallel with said sub data lines.

Claim 30

A semicodnuctor circuit according to claim 21, further comprising a plurality of sense amplifiers each of which differentially amplifies signals of two of said data lines which are arranged in parallel so as to be capacitively coupled with said wiring leads equally.

Claim 31

A semiconductor circuit according to claim 21, wherein said memory cell is arranged at only one of two intersection points between said word line and said two data lines which have signals to be differentially amplified.

Claim 32

A semiconductor circuit comprising: a memory array comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; and a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a first logic circuit disposed inside the memory array which outputs at least one signal by at least one wiring lead formed of a conductive layer which is arranged so as to intersect said plurality of data lines, wherein said data lines are formed of a first layer of aluminum, said wiring leads are formed of a second layer of aluminum, and said word lines are formed of a material which can be used in a self-alignment process.

Claim 33

A semiconductor circuit comprising: a memory array comprising: a plurality of data lines; a plurality of word lines which are arranged so as to intersect said plurality of data lines; a plurality of memory cells which are disposed at intersection points between said plurality of data lines and said plurality of word lines; a row decoder which selects at least one from among said plurality of word lines; and a column decoder which generates a signal for connecting one of said plurality of data lines to a common line; and a first logic circuit disposed inside the memory array which outputs at least one signal by at least one wiring lead formed of a conductive layer which is arranged so as to intersect said plurality of data lines, wherein said data lines are formed of a first layer of aluminum, said wiring leads are formed of a second layer of aluminum, and said word lines are formed of a material which can be used in a self-alignment process.