Integrated logic circuit having interconnections of various lengths between field effect transistors of enhancement and depletion modes

Claim 1

An integrated circuit for the generation of at least one logic combination of applied logic input signals in a two-state logic system and comprising a semiconductor body having a part mainly of a first conductivity type, an array of insulated gate field effect transistors formed in said part and having gate electrodes self-registered with source and drain electrode regions, and a plurality of substantially parallel first conductive tracks which comprise the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions of a second conductivity type opposite to that of the first which adjoin a surface of the body and cross the first conductive tracks, said transistors being formed at the crossings, said surface regions comprising the source and drain electrode regions of said transistors, a first group of the transistors being transistors of a first form having a first threshold voltage and a second group of the transistors being transistors of a second form having a second threshold voltage different from the first, said logic input signals in operation being applied to the gate electrodes of the transistors of one of said first and second groups of transistors, said logic combination to be generated being predetermined by the crossings and the form of transistor present at each such crossing and by the interconnections of transistors of said one of said first and second groups via the second conductivity type strip-shaped surface regions, the array being a nonuniform array in which at least one of the plurality first conductive tracks and the plurality of strip-shaped surfaces regions are not all of the same length, said logic combination further being predetermined by further interconnections formed within the array, and said further interconnections comprising at least a branching of a selected strip-shaped region.