US4037242A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device
Assignee: Texas Instruments Inc
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Filing: 1975-12-29
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Granted: 1977-07-19
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Expires: 1995-12-29
Abstract
Abstract A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.
Inventors
- 👤 William Milton Gosney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:37
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; H10D84/00; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
75 words
A semiconductor memory device having a monocrystalline semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate, electron injection means in said substrate at least partially underlying said gate, hole injection means in said substrate spaced from said electron injector means and at least partially underlying said gate, and means for sensing the presence or absence of charge on said gate, wherein said hole injection means comprises an n+/p- junction.
Claim 2
Dependent Claim
75 words
A semiconductor memory device having a monocrystalline semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate, electron injection means in said substrate at least partially underlying said gate, hole injection means in said substrate spaced from said electron injector means and at least partially underlying said gate, and means for sensing the presence or absence of charge on said gate, wherein said hole injection means comprises an n+/p- junction.
Claim 3
Dependent Claim
55 words
A device as in claim 1 wherein said n+/p- junction comprises an n+ region having a surface dopant concentration of at least 10 18 atoms/cc in said substrate, adjacent a p- region having a surface dopant concentration less than 10 17 atoms per cc, forming a semiconductor junction at least partially underlying said floating gate.
Claim 4
Dependent Claim
36 words
A device as in claim 1 wherein said hole injection means also comprises a capacitor of which a portion of said gate is one plate, and a p-type region in said substrate is the other plate.
Claim 5
Dependent Claim
161 words
A semiconductor memory device comprising: a. a monocrystalline semiconductor substrate of one conductivity type; b. an adherent layer of insulating material covering one surface thereof; c. an adherent electrically isolated floating gate conductor layer on said insulating material; d. means in said substrate for injecting electrons into and through said insulating layer for capture and storage on said gate; e. means in said substrate for injecting holes into and through said insulating layer for neutralizing stored charge in said gate; f. means in said substrate for sensing the presence or absence of charge in said gate; and g. a capacitor for assisting the injection of holes into and through said insulating layer, said capacitor comprising a portion of said gate as one capacitor plate, and a substrate region of opposite conductivity type as the other plate, at least partially underlying said portion of the gate, said plates being separated by a portion of said insulating layer serving as the capacitor dielectric.
Claim 6
Dependent Claim
161 words
A semiconductor memory device comprising: a. a monocrystalline semiconductor substrate of one conductivity type; b. an adherent layer of insulating material covering one surface thereof; c. an adherent electrically isolated floating gate conductor layer on said insulating material; d. means in said substrate for injecting electrons into and through said insulating layer for capture and storage on said gate; e. means in said substrate for injecting holes into and through said insulating layer for neutralizing stored charge in said gate; f. means in said substrate for sensing the presence or absence of charge in said gate; and g. a capacitor for assisting the injection of holes into and through said insulating layer, said capacitor comprising a portion of said gate as one capacitor plate, and a substrate region of opposite conductivity type as the other plate, at least partially underlying said portion of the gate, said plates being separated by a portion of said insulating layer serving as the capacitor dielectric.
Claim 7
Dependent Claim
24 words
A device as in claim 4 wherein said hole injection means comprises a n+/p- junction in said substrate at least partially underlying said gate.
Claim 8
Dependent Claim
18 words
A device as in claim 4 wherein said substrate is n-type and said semiconductor capacitor plate is p-type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |