Semiconductor memory device

Claim 2

A semiconductor memory device, comprising: N memory cell groups, which groups are obtained by dividing a memory cell array into N parts formed by arranging memory cells in matrix form; memory cell group selecting lines for selecting one of said memory cell groups; row decoders for decoding the row address data of a memory cell group to be accessed; front-end word lines connected to the output terminals of said row decoders, respectively. AND gates for ANDing selecting signals on said memory cell group selecting lines and output signals of said front-end word lines; and word lines connected to the output terminals of said AND gates, respectively.

Claim 3

A device as claimed in claim 1, wherein said frontend word lines are lower in resistance than said word lines.

Claim 4

A device as claimed in claim 1, wherein said word lines and said front-end word lines are arranged in parallel to one another.

Claim 5

A device as claimed in claim 1, said row decoders being arranged at one side of said N memory cell groups.

Claim 6

A device as claimed in claim 1, said memory cell groups being arranged in the form of columns.

Claim 7

A device as claimed in claim 1, said word lines and said front-end word lines each being arranged perpendicular to the direction of said columns. .Iadd.

Claim 8

A semiconductor memory device, comprising: memory cell array arranged in a matrix of rows and columns of memory cells, said memory cell array being divided into a plurality of groups of memory cells, each group comprising a submatrix of said memory cells, each submatrix comprising a plurality of divided row lines for activating respective rows of said memory cells within said submatrix, one divided row line being provided for each row of memory cells within said submatrix; memory cell group selecting lines for selecting one of said memory cell groups for access, one of said memory cell group selecting lines being provided for each of said memory cell groups; row decoders for decoding row address data to select a row of said matrix to be accessed; a plurality of front-end word lines extending over said memory cell groups, each of said front-end word lines being connected to an output of a respective one of said row decoders; and means for activating said divided row lines in response to activation of corresponding ones of said memory cell group selecting lines and said front-end word lines..Iaddend. .Iadd.8. The semiconductor memory device as claimed in claim 7, wherein said activating means further comprises a plurality of AND gates, one of said AND gates being provided for each of said divided word lines, each of said AND gates having a first input connected to respective one of said memory cell group selecting lines and a second input connected to a respective one of said front-end word

Claim 9

lines..Iaddend. .Iadd.9. The semiconductor memory device as claimed in 7, wherein said front-end word lines are lower in resistance than said word lines..Iaddend. .Iadd.10. The semiconductor memory device as claimed in claim 7, wherein said word lines and said front-end word lines are arranged in parallel to one another..Iaddend. .Iadd.11. The semiconductor memory device as claimed in claim 7, wherein said row decoders are arranged at one side of said N memory cell groups..Iaddend. .Iadd.12. The semiconductor memory device as claimed in claim 7, wherein said memory cell groups are arranged in the form of columns..Iaddend. .Iadd.13. The semiconductor memory device as claimed in claim 7, wherein said word lines and said front-end word lines are each arranged perpendicular to the direction of said columns..Iaddend.