EP0068645A2
Expired / Lapsed
EP
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A semiconductor device
Assignee: Hitachi Ltd
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Filing: 1982-05-28
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Granted: —
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Expires: 2002-05-28
Abstract
Abstract A semiconductor memory having a structure wherein each of data lines [D<sub>0</sub>] intersecting word lines (W<sub>i</sub>) is divided into a plurality of sub lines in its lengthwise direction, memory cells (MC) are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines (1/0) are arranged in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements (SW), and the switching elements are connected to a decoder (Y) through control lines (YC) and are selectively driven by control signals (0y) generated from the decoder.
Inventors
- 👤 Kiyoo Itoh
- 👤 Ryoichi Hori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/408; G11C11/4087; G11C11/4097; G11C5/00; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
235 words
A semiconductor memory having a memory array consisting of a plurality of memory cells (MC) each of which includes a charge storage portion (C ) and first switching means (Q) having its one end connected to the charge storage portion; characterised in that the semiconductor memory comprises (a) a plurality of word lines (W.) which are arranged in one direction on said memory array and which are respectively connected to gates of the first switching means (Q); (b) a first decoder (X) which selectively drives said plurality of word lines; (c) a plurality of input/output lines (D O , DO ) which are arranged in a direction intersecting said plurality of word lines, to which the other ends of said first switching means are respectively connected and each of which is divided into a plurality of sub lines in its lengthwise direction; (d) a plurality of common input/output lines (I/O) each of which is arranged in common to at least two of said sub lines and which are connected to said sub lines through second switching means (SW); (e) a plurality of control lines (YC) which are connected to gates of said second switching means (SW); (f) a second decoder (Y) which selectively drives said plurality of control lines; and (g) read/write control means (30) to control reading and writing of information of said memory cells through said common input/output lines and said input/output lines.
Claim 2
Dependent Claim
235 words
A semiconductor memory having a memory array consisting of a plurality of memory cells (MC) each of which includes a charge storage portion (C ) and first switching means (Q) having its one end connected to the charge storage portion; characterised in that the semiconductor memory comprises (a) a plurality of word lines (W.) which are arranged in one direction on said memory array and which are respectively connected to gates of the first switching means (Q); (b) a first decoder (X) which selectively drives said plurality of word lines; (c) a plurality of input/output lines (D O , DO ) which are arranged in a direction intersecting said plurality of word lines, to which the other ends of said first switching means are respectively connected and each of which is divided into a plurality of sub lines in its lengthwise direction; (d) a plurality of common input/output lines (I/O) each of which is arranged in common to at least two of said sub lines and which are connected to said sub lines through second switching means (SW); (e) a plurality of control lines (YC) which are connected to gates of said second switching means (SW); (f) a second decoder (Y) which selectively drives said plurality of control lines; and (g) read/write control means (30) to control reading and writing of information of said memory cells through said common input/output lines and said input/output lines.
Claim 3
Dependent Claim
37 words
A semiconductor memory according to claim 1 characterised in that each of said plurality of input/ output lines (D 0 , DO ) is formed by pair lines which are simultaneously selected and which are differentially read/written.
Claim 4
Dependent Claim
50 words
A semiconductor memory according to claim 2, characterised in that said plurality of common input/ output lines (I/O) are arranged in a direction intersecting said plurality of input/output lines (D 0 , D) and said plurality of control lines (YC) are arranged in parallel with said plurality of input/output lines.
Claim 5
Dependent Claim
39 words
A semiconductor memory according to claim 3, characterised in that principal parts of said plurality of control lines (YC) are formed of a layer different from that of principal parts of said input/output lines (D 0 , DO ).
Claim 6
Dependent Claim
43 words
A semiconductor memory according to claim 3, characterised in that either of said word lines (W.) and said input/output lines (D . , D 0 ) is formed of a first metal, and said control lines (YC) are formed of a second metal.
Claim 7
Dependent Claim
23 words
A semiconductor memory according to claim 5 characterised in that said first metal is doped polycrystalline silicon, and said second metal is aluminium.
Claim 8
Dependent Claim
32 words
A semiconductor memory according to claim 3, characterised in that each of said control lines (YC) is arranged in correspondence with the paired input/ output lines (D 0 , D 0 ).
Claim 9
Dependent Claim
18 words
A semiconductor memory according to claim 7 characterised in that said pair input/output lines intersect each other midway.
Claim 10
Dependent Claim
23 words
A semiconductor memory according to claim 7 characterised in that said control lines intersect said input/output lines at the respective divided sub lines.
Claim 11
Dependent Claim
44 words
A semiconductor memory according to claim 1, characterised in that said plurality of common input/ output lines are arranged in parallel with said plurality of input/output lines, and said plurality of control lines are arranged in a direction intersecting said plurality of input/output lines.
References Cited (Backward Citations)
No citation records indexed.
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