Charge pumping semiconductor memory

Claim 2

A semiconductor memory cell comprising: a semiconductor substrate of one conductivity type; first to eighth semiconductor regions of opposite conductivity type formed in the surface region of said semiconductor substrate; gate means formed of polycrystalline silicon and including a first gate electrode insulatively disposed at least in part above said first and second semiconductor regions to control electrical current flowing between said first and second semiconductor regions, a second gate electrode insulatively disposed at least in part above said third and fourth semiconductor regions to control electrical current flowing between said third and fourth semiconductor regions, and a third gate electrode insulatively disposed at least in part above said fifth to eighth semiconductor regions to control electrical current flowing between said fifth and sixth semiconductor regions and at the same time control electrical current flowing between said seventh and eighth semiconductor regions; first and second capacitor electrodes formed of a polycrystalline silicon layer, said first capacitor electrode being insulatively disposed above a first part of said semiconductor substrate which lies adjacent to said first semiconductor region, and said second capacitor electrode being insulatively disposed above a second part of said semiconductor substrate which lies adjacent to said third semiconductor region; first coupling means for electrically coupling said first and fifth semiconductor regions to said second gate electrode; and second coupling means for electrically coupling said third and seventh semiconductor regions to said first gate electrode; wherein said first and second semiconductor regions and said first gate electrode constitute a first driver transistor; said third and fourth semiconductor regions and said second gate electrode constitute a second driver transistor; said fifth and sixth semiconductor regions and said third gate electrode constitute a first address selection transistor; said seventh and eighth semiconductor regions and said third gate electrode consitute a second address selection transistor; said first part of the semiconductor substrate and said first capacitor electrode constitute a first load capacitor; and said second part of the semiconductor substrate and said second capacitor electrode constitute a second load capacitor and said first gate electrode and said first capacitor electrode are disposed to overlap each other lnsulatively and at least partly.

Claim 3

A semiconductor memory cell according to claim 1, wherein said first conductivity type is a p-type.

Claim 4

A semiconductor memory cell according to claim 1 or 2, wherein said first and fifth semiconductor regions and said first coupling means are formed of a same semiconductor material.

Claim 5

A semiconductor memory cell according to claim 1 or 2, wherein said second coupling means includes a first coupling semiconductor region formed as part of said third semiconductor region and a second coupling semiconductor region formed as part of said seventh semiconductor region.

Claim 6

A semiconductor memory apparatus comprising: a plurality of memory cells arranged in a matrix array and each including first to eighth semiconductor regions of opposite conductivity type formed in the surface region of said semiconductor substrate, gate means formed of polycrystalline silicon and including first gate electrode insulatively disposed at least in part above said first and second semiconductor regions to control electrical current flowing between said first and second semiconductor regions, second gate electrode insulatively disposed at least in part above said third and fourth semiconductor regions to control electrical current flowing between said third and fourth semiconductor regions and third gate electrode insulatively disposed at least in part above said fifth to eighth semiconductor regions to control electrical current flowing between said fifth and sixth semiconductor regions and at the same time control electrical current flowing between said seventh and eighth semiconductor regions, first and second capacitor electrodes formed of a polycrystalline silicon layer, said first capacitor electrode being insulatively disposed above a first part of said semiconductor substrate which lies adjacent to said first semiconductor region and said second capacitor electrode being insulatively disposed above a second part of said semiconductor substrate which lies adjacent to said third semiconductor region, said first gate electrode and said first capacitor electrode are disposed to overlap each other insulatively and at least partly, first coupling means for electrically coupling said first and fifth semiconductor regions to said second gate electrode, and second coupling means for electrically coupling said third and seventh semiconductor regions to said first gate electrode, wherein the memory cells in each row have the same pattern and are formed symmetrical with those in the adjacent row, and said third gate electrodes of the memory cells in the same row are formed of a single polycrystalline silicon layer extending in a row direction; a plurality of first conductive layers which are arranged in a column direction and each of which electrically connects the second semiconductor regions of the memory cells in a first column and the fourth semiconductor regions of memory cells in one of two columns adjacent to the first column; a plurality of second conductive layers which are arranged in a column direction and each of which electrically connects the sixth semiconductor regions of memory cells in a column; a plurality of third conductive layers which are arranged in a column direction and each of which electrically connects the eight semiconductor regions of memory cells in a column; a word driver circuit connected to the third gate electrodes arranged in each row to selectively energize the third gate electrode; a sense amplifier and write drive circuit connected to said second and third conductive layers arranged in each column to selectively energize the second and third layers; control means supplying address signals to said word drive circuit and sense amplifier and write driver circuit to select the row and column; and clock pulse generating means connected to said first and second capicator electrodes in each memory cell to supply a clock pulse signal to each of said first and second capacitor electrodes.

Claim 7

A semiconductor memory apparatus comprising: a plurality of memory cells arranged in a matrix array and each including first to eighth semiconductor regions of opposite conductivity type formed in the surface region of said semiconductor substrate, gate means formed of polycrystalline silicon and including first gate electrode insulatively disposed at least in part above said first and second semiconductor regions to control electrical current flowing between said first and second semiconductor regions, second gate electrode insulatively disposed at least in part above said third and fourth semiconductor regions to control electrical current flowing between said third and fourth semiconductor regions and third gate electrode insulatively disposed at least in part above said fifth to eighth semiconductor regions to control electrical current flowing between said fifth and sixth semiconductor regions and at the same time control electrical current flowing between said seventh and eighth semiconductor regions, first and second capacitor electrodes formed of a polycrystalline silicon layer, said first capacitor electrode being insulatively disposed above a first part of said semiconductor substrate which lies adjacent to said first semiconductor region and said second capacitor electrode being insulatively disposed above a second part of said semiconductor substrate which lies adjacent to said third semiconductor region, said first gate electrode and said first capacitor electrode are disposed to overlap each other insulatively and at least partly, first coupling means for electrically coupling said first and fifth semiconductor regions to said second gate electrode, and second coupling means for electrically coupling said third and seventh semiconductor regions to said first gate electrode, wherein the memory cells in each row have the same pattern and are formed symmetrical with those in the adjacent row, and said third gate electrodes of the memory cells in the same row are formed of a single polycrystalline silicon layer extending in a row direction; a plurality of first conductive layers which are arranged in a column direction and each of which electrically connects the second semiconductor regions of the memory cells in a first column and the fourth semiconductor regions of memory cells in one of two columns adjacent to the first column; a plurality of second conductive layers which are arranged in a column direction and each of which electrically connects the sixth semiconductor regions of memory cells in a column; a plurality of third conductive layers which are arranged in a column direction and each of which electrically connects the eight semiconductor regions of memory cells in a column; a word driver circuit connected to the third gate electrodes arranged in each row to selectively energize the third gate electrode; a sense amplifier and write drive circuit connected to said second and third conductive layers arranged in each column to selectively energize the second and third layers; control means supplying address signals to said word drive circuit and sense amplifier and write driver circuit to select the row and column; and clock pulse generating means connected to said first and second capicator electrodes in each memory cell to supply a clock pulse signal to each of said first and second capacitor electrodes.

Claim 8

A semiconductor memory apparatus according to claim 5, wherein those of said first and second capacitor electrodes which are formed in each of the memory cells arranged in two adjacent rows are formed of a single polycrystalline silicon layer.

Claim 9

A semiconductor memory apparatus according to claim 5, wherein said clock pulse generating means is constituted by a plurality of metal-oxide-semiconductor transistors formed on a chip on which said memory cells are formed.

Claim 10

A semiconductor memory apparatus according to claim 5, 6 or 7, further comprising a self-back-gate-bias circuit connected between the output terminal of said clock pulse generating means and said semiconductor substrate to transfer electric charges to said semiconductor substrate.

Claim 11

A semiconductor memory apparatus according to claim 8, wherein said self-back-gate-bias circuit includes first and second diodes connected between said semiconductor substrate and a reference potential point; and an metal-oxide-semiconductor capacitor connected between the junction of said first and second diodes and the output terminal of said clock pulse generator.

Claim 12

A semiconductor memory apparatus according to claim 8 wherein said self-back-gate-bias circuit includes first and second metal-oxide-semiconductor transistors whose current paths are connected between said semiconductor substrate and a reference potential point, said first metal-oxide-semiconductor transistor having the gate connected to the semiconductor substrate and said second metal-oxide-semiconductor transistor having the gate connected to the drain of said first metal-oxide-semiconductor transistor, and an metal-oxide-semiconductor capacitor connected between the junction of said first and second metal-oxide-semiconductor transistors and the output terminal of said clock pulse generating means.

Claim 13

A semiconductor memory apparatus according to claim 5, wherein said first and fifth semiconductor regions and said first coupling means in each memory cell are formed of a semiconductor material.

Claim 14

A semiconductor memory apparatus according to claim 5, wherein said second coupling means includes a first coupling semiconductor region formed as part of said third semiconductor region and a second coupling semiconductor region formed as part of said seventh semiconductor region.