Integrated circuit bistable memory cell using charge-pumped devices

Claim 2

In a bistable memory cell suitable for fabrication by integrated circuit technology comprising first and second conducting layer-insulating layer-semiconductor field-effect transistors each having a drain electrode cross coupled to the gate electrode of the other transistor and having source electrodes connected to a common potential, and third and fourth conducting layer-insulating layer-semiconductor field-effect charge-transfer active devices having source electrodes connected respectively to the drain electrodes of said first and second transistors and having gate electrodes adapted to be connected to a source of repetitive variable voltage having a peak magnitude exceeding the threshold voltage of said charge-transfer devices, said third and fourth chargetransfer devices each having only a single doped region, a resultant switching of the charge-transfer devices gate voltage above and below the threshold voltage in response to the repetitive variable voltage causing transfer of charge from the source electrodes thereof to the semiconductor regions thereof to thereby develop currents of magnitude dependent on the frequency of the gate applied voltage.

Claim 3

In the bistable memory cell set forth in claim 1 and further comprising accessing means connected to a first circuit node defined by the drain-source juncture of the first transistor and third charge-transfer device and to a second circuit node defined by the drain-source juncture of the second transistor and fourth charge-transfer device for addressing the memory cell.

Claim 4

In the bistable memory cell set forth in claim 1 wherein said first transistor and said third charge-transfer device are of the same conductivity type, and said second transistor and said fourth charge-transfer device are of the same conductivity type.

Claim 5

In the bistable memory cell set forth in claim 1 wherein said first and second transistors and said third and fourth charge-transfer devices are all of the same conductivity type.

Claim 6

In the bistable memory cell set forth in claim 4 wherein said first and second transistors and said third and fourth charge-transfer devices are of the p-conductivity type.

Claim 7

In the bistable memory cell set forth in claim 4 wherein said first and seconD transistors and said third and fourth charge-transfer devices are of the n-conductivity type.

Claim 8

In the bistable memory cell set forth in claim 1 wherein said first and second transistors and said third and fourth charge-transfer devices are formed on a common semiconductor substrate, the single doped regions of said third and fourth charge-transfer devices are formed in the substrate and form the source electrodes of the charge-transfer devices.

Claim 9

In the bistable memory cell set forth in claim 7 wherein a first and second of the doped regions of said third and fourth charge-transfer devices also respectively forming the drain electrodes of said first and second transistors to thereby provide the charge-transfer device source electrode to transistor drain electrode connections.

Claim 10

In the bistable memory cell set forth in claim 8 wherein said first and second transistors having a common third doped region formed in the substrate, the third doped region forming the source electrodes of the first and second transistors, the first, second and third doped regions being spaced from each other and being of the same conductivity type.

Claim 11

In the bistable memory cell set forth in claim 9 wherein an insulating layer overlying a surface of the substrate, a first patterned conducting layer overlying a first portion of the insulating layer and having a first end formed through the insulating layer and contacting the first doped region and having a second end overlying a substrate region separating the second and third doped regions to thereby form the gate electrode of the second transistor, the first patterned conducting layer providing the coupling of the drain electrode of the first transistor to the gate electrode of the second transistor, and a second patterned conducting layer overlying a second portion of the insulating layer and having a first end formed through the insulating layer and contacting the second doped region and having a second end overlying a substrate region separating the first and third doped regions to thereby form the gate electrode of the first transistor, the second patterned conducting layer providing the coupling of the drain electrode of the second transistor to the gate electrode of the first transistor.

Claim 12

In the bistable memory cell set forth in claim 10 wherein a third patterned conducting layer overlying a third portion of the insulating layer which overlies portions of the first and second doped regions to thereby form the gate electrodes of said third and fourth charge-transfer devices.

Claim 13

A charge-pumped active resistor device suitable for fabrication by integrated circuit technology comprising a semiconductor substrate, a single doped region of conductivity type opposite that of said substrate and formed therein, an insulating gate layer formed over the substrate and doped region, and a conducting gate layer formed over a portion of the insulating gate layer which is in communication with the doped region, said conducting gate layer provided with terminal means adapted for connection to a source of repetitive variable voltage having a peak magnitude exceeding the threshold voltage of the charge-pumped device, a resultant switching of the charge-pumped device gate voltage above and below the threshold voltage in response to the repetitive variable voltage causing transfer of charge from the doped region to the semiconductor substrate to thereby generate a doped region-to-substrate current of magnitude dependent on the frequency of the gate applied voltage, the variable current generating ability of the charge-pumped device thereby producing an equivalent active resistor device which may be controlled and have high resistance value for a small physical size of the device.

Claim 14

A charge-pumped active resistor device suitable for fabrication by integrated circuit technology comprising a semiconductor substrate, a single doped region of conductivity type opposite that of said substrate and formed therein, an insulating gate layer formed over the substrate and doped region, and a conducting gate layer formed over a portion of the insulating gate layer which is in communication with the doped region, said conducting gate layer provided with terminal means adapted for connection to a source of repetitive variable voltage having a peak magnitude exceeding the threshold voltage of the charge-pumped device, a resultant switching of the charge-pumped device gate voltage above and below the threshold voltage in response to the repetitive variable voltage causing transfer of charge from the doped region to the semiconductor substrate to thereby generate a doped region-to-substrate current of magnitude dependent on the frequency of the gate applied voltage, the variable current generating ability of the charge-pumped device thereby producing an equivalent active resistor device which may be controlled and have high resistance value for a small physical size of the device.