US5343406A
Expired / Lapsed
US
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Distributed memory architecture for a configurable logic array and method for using distributed memory
Assignee: Xilinx Inc
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Filing: 1989-07-28
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Granted: 1994-08-30
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Expires: 2009-07-28
Abstract
Abstract Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.
Inventors
- 👤 Ross H. Freeman
- 👤 Hung-Cheng Hsieh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
68 words
A configurable logic array having a configurable logic block comprising a memory cell, said memory cell being electrically connected by a first address line to a first data line for receiving a first data signal during initial configuration of said configurable logic block, and electrically connected by a second address line to a second data line for receiving second data signals during operation of said configurable logic array.
Claim 2
Dependent Claim
68 words
A configurable logic array having a configurable logic block comprising a memory cell, said memory cell being electrically connected by a first address line to a first data line for receiving a first data signal during initial configuration of said configurable logic block, and electrically connected by a second address line to a second data line for receiving second data signals during operation of said configurable logic array.
Claim 3
Dependent Claim
94 words
A configurable logic array comprising: a plurality of configurable logic blocks, each configurable logic block having at least two inputs; a plurality of memory cells associated with each of said configurable logic blocks; a plurality of configuration lines; a plurality of interconnect lines, said interconnect lines being connectable to each other and to said inputs; first means for writing to all of said memory cells in a logic block through said configuration lines; and second means for writing to at least some of said memory cells in said logic block through said interconnect lines.
Claim 4
Dependent Claim
94 words
A configurable logic array comprising: a plurality of configurable logic blocks, each configurable logic block having at least two inputs; a plurality of memory cells associated with each of said configurable logic blocks; a plurality of configuration lines; a plurality of interconnect lines, said interconnect lines being connectable to each other and to said inputs; first means for writing to all of said memory cells in a logic block through said configuration lines; and second means for writing to at least some of said memory cells in said logic block through said interconnect lines.
Claim 5
Dependent Claim
41 words
A configurable logic array as in claim 2 in which said second means for writing to at least some of said memory cells after configuration of said configurable logic block is under control of logic programmed into said configurable logic array.
Claim 6
Dependent Claim
26 words
A configurable logic array as in claim 2 in which each of said memory cells includes two nodes for providing output signals complementary to each other.
Claim 7
Dependent Claim
25 words
A configurable logic array as in claim 2 in which said memory cells are grouped to form a truth table for a desired logic function.
Claim 8
Dependent Claim
74 words
A configurable logic array as in claim 4 in which said first means for writing to each of said memory cells includes a first access line electrically connectable to a first one of said plurality of configuration lines and a first pass transistor having a control terminal connected to a second one of said plurality of configuration lines for allowing said memory cell to be read or written to on said first access line.
Claim 9
Dependent Claim
73 words
A configurable logic array as in claim 6 in which said second means for writing to at least some of said memory cells comprises a second access line connectable to a first one of said plurality of interconnect lines and a second pass transistor having a control terminal connectable to a second one of said plurality of interconnect lines for allowing said memory cell to be written to on said second access line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |