US5459421A — Dynamic-static master slave flip-flop circuit

Claim 1

Independent Claim 100 words

A flip-flop circuit comprising: a dynamic master portion containing a first circuit for storing a signal state, said first circuit storing said signal state by maintaining a charge state representing said signal state; and a static slave portion coupled to and responsive to said master portion containing a second circuit for storing a signal state, said second circuit storing said signal state by switching to a voltage potential representing said signal state. a clock line coupled to said master portion and said slave portion, said clock line carrying a clock signal to control said master portion and said slave portion.

Claim 2

Dependent Claim 100 words

A flip-flop circuit comprising: a dynamic master portion containing a first circuit for storing a signal state, said first circuit storing said signal state by maintaining a charge state representing said signal state; and a static slave portion coupled to and responsive to said master portion containing a second circuit for storing a signal state, said second circuit storing said signal state by switching to a voltage potential representing said signal state. a clock line coupled to said master portion and said slave portion, said clock line carrying a clock signal to control said master portion and said slave portion.

Claim 3

Dependent Claim 53 words

The circuit of claim 1 wherein said master portion further comprises an input device for maintaining charge states on a first node in response to an input signal and a clock signal, said input device also maintaining charge states on a second node in response to said input signal and said clock signal.

Claim 4

Dependent Claim 59 words

The circuit of claim 2 wherein said input device is comprised of: a first p channel transistor with a source coupled to a high voltage potential; a pass gate coupled to said first p channel transistor; and a first n channel transistor with a drain coupled to said pass gate and a source coupled to a low voltage potential.

Claim 5

Dependent Claim 53 words

The circuit of claim 3 wherein said pass gate is comprised of: a second p channel transistor with a gate coupled to a first clock line; and a second n channel transistor with a source and drain coupled to said second p channel transistor and a gate coupled to a second clock line.

Claim 6

Dependent Claim 51 words

The circuit of claim 2 wherein said input device is comprised of: a p logic unit; a pass gate coupled to said p logic unit; a n logic unit coupled to said pass gate; and said p logic unit and said n logic unit for incorporating logic functions into said circuit.

Claim 7

Dependent Claim 78 words

The circuit of claim 1 wherein said master portion further comprises of: an input device for applying a charge state to a first node and a second node in response to a first signal state when a clock signal is in a first clock state, said input device applying a second charge state to said first node and said second node in response to a second signal state when said clock signal is in said first clock state.

Claim 8

Dependent Claim 90 words

The circuit of claim 1 wherein said master portion further comprises of: an input device for applying a charge state to a first node and maintaining an existing charge state on a second node in response to a first signal state when a clock signal is in a second clock state, said input device maintaining a previous charge state on said first node and applying a second charge state to said second node in response to a second signal state when said clock signal is in said second clock state.

Claim 9

Dependent Claim 28 words

The circuit of claim 1 wherein said master portion further comprises of: a control device for transmitting a signal in response to a charge state on a node.

Claim 10

Dependent Claim 48 words

The circuit of claim 8 wherein said control device is comprised of: a p channel transistor with a source coupled to a high voltage potential; and a n channel transistor with a source coupled to said p channel transistor and a drain coupled to a low voltage potential.

Claim 11

Dependent Claim 87 words

The circuit of claim 1 wherein said master portion further comprises of: a control device for transmitting a first signal state when a first node and a second node are both in a first charge state, said control device transmitting a second signal state when said first node and said second node are both in a second charge state, said output device maintaining a previous signal state when said first node is in said first charge state and said second node is in said second charge state.

Claim 12

Dependent Claim 42 words

The circuit of claim 1 wherein said slave portion further comprises of: a pass gate preventing a signal to pass in response to a first clock state, said pass gate allowing said signal to pass in response to a second clock state.

Claim 13

Dependent Claim 50 words

The circuit of claim 11 wherein said pass gate is comprised of: a p channel transistor with a gate coupled to a first clock line; and a n channel transistor with a source and drain coupled to said p channel transistor and a gate coupled to a second clock line.

Claim 14

Dependent Claim 49 words

The circuit of claim 1 wherein said slave portion further comprises of: a first inverter coupled to a pass gate, said first inverter positioned in a first direction; and a second inverter coupled to said pass gate and said first inverter, said second inverter positioned in a second direction.

Claim 15

Dependent Claim 46 words

The circuit of claim 11 wherein said second inverter causes a third node to switch to a first voltage potential in response to a first signal state and causes said third node to switch to a second voltage potential in response to a second signal state.

Claim 16

Dependent Claim 97 words

The circuit of claim 13 wherein said first inverter comprises of a clocked inverter, said clocked inverter applying a first voltage potential to a fourth node in response to a second voltage potential on a third node when a clock signal is in a first clock state, said clocked inverter applying a second voltage potential to a fourth node in response to a first voltage potential on a third node when said clock signal is in said first clock state, said clocked inverter isolating a fourth node when said clock signal is in a second clock state.

Claim 17

Dependent Claim 117 words

The circuit of claim 15 wherein said clocked inverter is comprised of: a first p channel transistor with a source coupled to a high voltage potential; a second p channel transistor with a source coupled to said first p channel transistor and a gate coupled to a first clock line; a first n channel transistor with a drain coupled to a drain of said second p channel transistor and a gate coupled to a second clock line; and a second n channel transistor with a drain coupled to a source of said first n channel transistor, a source coupled to a low voltage potential and a gate coupled to a gate of said first p channel transistor.

Claim 18

Dependent Claim 52 words

The circuit of claim 13 wherein said first inverter and said second inverter further comprises of: a p channel transistor with a source coupled to a high voltage potential; and a n channel transistor with a drain coupled to said p channel transistor and a source coupled to a low voltage potential.

Claim 19

Dependent Claim 54 words

The circuit of claim 1 wherein said slave portion further comprises of: a third inverter coupled to a pass gate and coupled to an output line, said third inverter outputting a first signal state in response to a second signal state and outputting said second signal state in response to said first signal state.

Claim 20

Dependent Claim 22 words

The circuit of claim 1 wherein said circuit further comprises a delay circuit to delay a clock signal to said master portion.

Claim 21

Independent Claim 46 words

A method for storing signals in a flip-flop circuit comprising: storing a signal state in a master portion by maintaining a charge state representing said signal state; and storing said signal state in a slave portion by switching to a voltage potential representing said signal state.

Claim 22

Independent Claim 46 words

A method for storing signals in a flip-flop circuit comprising: storing a signal state in a master portion by maintaining a charge state representing said signal state; and storing said signal state in a slave portion by switching to a voltage potential representing said signal state.

Claim 23

Dependent Claim 46 words

The method of claim 20 wherein said method further comprises of: maintaining charge states on a first node in response to an input signal and a clock signal; and maintaining charge states on a second node in response to said input signal and said clock signal.

Claim 24

Dependent Claim 72 words

The method of claim 20 wherein said method further comprises of: applying a first charge state to a first node and a second node in response to a first signal state when a clock signal is in a first clock state; and applying a second charge state to said first node and said second node in response to a second signal state when said clock signal is in said first clock state.

Claim 25

Dependent Claim 84 words

The method of claim 20 wherein said method further comprises of: applying a first charge state to a first node and maintaining a previous charge state on a second node in response to a first signal state when a clock signal is in a second clock state; and maintaining a previous charge state on said first node and applying a second charge state to said second node in response to a second signal state when said clock signal is in said second clock state.

Claim 26

Dependent Claim 23 words

The method of claim 20 wherein said method further comprises of: transmitting a signal in response to a charge state on a node.

Claim 27

Dependent Claim 77 words

The method of claim 20 wherein said method further comprises of: outputting a first signal state when a first node and a second node are both in a first charge state; outputting a second signal state when said first node and said second node are both in a second charge state; and maintaining a previous signal state when said first node is in said first charge state and said second node is in said second charge state.

Claim 28

Dependent Claim 36 words

The method of claim 20 wherein said method further comprises of: preventing a signal to pass in response to a first clock state; and allowing said signal to pass in response to a second clock state.

Claim 29

Dependent Claim 48 words

The method of claim 20 wherein said method further comprises of: causing a third node to switch to a first voltage potential in response to a first signal state; and causing said third node to switch to a second voltage potential in response to a second signal state.

Claim 30

Dependent Claim 85 words

The method of claim 20 wherein said method further comprises of: applying a first voltage potential to a fourth node in response to a second voltage potential on a third node when a clock signal is in a first clock state, applying a second voltage potential to a fourth node in response to a first voltage potential on a third node when said clock signal is in said first clock state, isolating a fourth node when said clock signal is in a second clock state.

Claim 31

Dependent Claim 36 words

The method of claim 20 wherein said method further comprises of: outputting a first signal state in response to a second signal state; and outputting said second signal state in response to said first signal state.

Claim 32

Dependent Claim 19 words

The method of claim 20 wherein said method further comprises of delaying a clock signal to said master portion.

Claim 33

Dependent Claim 62 words

A flip-flop circuit for storing signals comprising: a master means for storing a signal state, said master means storing said signal state by maintaining a charge state representing said signal state; and a slave means coupled to said master means for storing a signal state, said slave means storing said signal state by switching to a voltage potential representing said signal state.

Claim 34

Dependent Claim 62 words

A flip-flop circuit for storing signals comprising: a master means for storing a signal state, said master means storing said signal state by maintaining a charge state representing said signal state; and a slave means coupled to said master means for storing a signal state, said slave means storing said signal state by switching to a voltage potential representing said signal state.

Claim 35

Dependent Claim 54 words

The circuit of claim 31 wherein said master means further comprises of: an input means for maintaining charge states on a first node in response to an input signal and a clock signal, said input means also maintaining charge states on a second node in response to said input signal and said clock signal.

Claim 36

Dependent Claim 79 words

The circuit of claim 31 wherein said master means further comprises of: an input means for applying a first charge state to a first node and a second node in response to a first signal state when a clock signal is in a first clock state, said input means applying a second charge state to said first node and said second node in response to a second signal state when said clock signal is in said first clock state.

Claim 37

Dependent Claim 91 words

The circuit of claim 31 wherein said master means further comprises of: an input means for applying a first charge state to a first node and maintaining a previous charge state on a second node in response to a first signal state when a clock signal is in a second clock state, said input means maintaining a previous charge state on said first node and applying a second charge state to said second node in response to a second signal state when said clock signal is in said second clock state.

Claim 38

Dependent Claim 27 words

The circuit of claim 31 wherein said master means further comprises of: control means for transmitting a signal in response to a charge state on a node.

Claim 39

Dependent Claim 86 words

The circuit of claim 31 wherein said master means further comprises of: control means for transmitting a first signal state when a first node and a second node are both in a first charge state, said control means transmitting a second signal state when said first node and said second node are both in a second charge state, said control means maintaining a previous signal state when said first node is in said first charge state and said second node is in said second charge state.

Claim 40

Dependent Claim 45 words

The circuit of claim 31 wherein said slave means further comprises of: a pass gate means for preventing a signal to pass in response to a first clock state, said pass gate means allowing said signal to pass in response to a second clock state.

Claim 41

Dependent Claim 53 words

The circuit of claim 31 wherein said slave means further comprises of: an inverter means for causing a third node to switch to a first voltage potential in response to a first signal state and causing said third node to switch to a second voltage potential in response to a second signal state.

Claim 42

Dependent Claim 99 words

The circuit of claim 31 wherein said slave means further comprises of: a clocked inverter means for applying a first voltage potential to a fourth node in response to a second voltage potential on a third node when a clock signal is in a first clock state, said clocked inverter means applying a second voltage potential to a fourth node in response to a first voltage potential on a third node when said clock signal is in said first clock state, said clocked inverter means isolating a fourth node when said clock signal is in a second clock state.

Claim 43

Dependent Claim 42 words

The circuit of claim 31 wherein said slave means further comprises of: a third inverter means for outputting a first signal state in response to a second signal state and outputting said second signal state in response to said first signal state.

Claim 44

Dependent Claim 19 words

The circuit of claim 31 further comprising a delay means for delaying a clock signal to said master means.

Claim 45

Dependent Claim 16 words

The circuit of claim 31 further comprising logic means for incorporating logic functions into said circuit.

Claim 46

Dependent Claim 81 words

In a computer system having a processor and memory, a flip-flop circuit comprising: a dynamic master portion containing a first circuit for storing a signal state, said first circuit storing said signal state by maintaining a charge state representing said signal state; and a static slave portion coupled to and responsive to said master portion containing a second circuit for storing a signal state, said second circuit storing said signal state by switching to a voltage potential representing said signal state.

Claim 47

Dependent Claim 81 words

In a computer system having a processor and memory, a flip-flop circuit comprising: a dynamic master portion containing a first circuit for storing a signal state, said first circuit storing said signal state by maintaining a charge state representing said signal state; and a static slave portion coupled to and responsive to said master portion containing a second circuit for storing a signal state, said second circuit storing said signal state by switching to a voltage potential representing said signal state.

Claim 48

Dependent Claim 53 words

The circuit of claim 43 wherein said master portion further comprises an input device for maintaining charge states on a first node in response to an input signal and a clock signal, said input device also maintaining charge states on a second node in response to said input signal and said clock signal.

Claim 49

Dependent Claim 59 words

The circuit of claim 44 wherein said input device is comprised of: a first p channel transistor with a source coupled to a high voltage potential; a pass gate coupled to said first p channel transistor; and a first n channel transistor with a drain coupled to said pass gate and a source coupled to a low voltage potential.

Claim 50

Dependent Claim 53 words

The circuit of claim 45 wherein said pass gate is comprised of: a second p channel transistor with a gate coupled to a first clock line; and a second n channel transistor with a source and drain coupled to said second p channel transistor and a gate coupled to a second clock line.

Claim 51

Dependent Claim 51 words

The circuit of claim 44 wherein said input device is comprised of: a p logic unit; a pass gate coupled to said p logic unit; a n logic unit coupled to said pass gate; and said p logic unit and said n logic unit for incorporating logic functions into said circuit.

Claim 52

Dependent Claim 78 words

The circuit of claim 43 wherein said master portion further comprises of: an input device for applying a charge state to a first node and a second node in response to a first signal state when a clock signal is in a first clock state, said input device applying a second charge state to said first node and said second node in response to a second signal state when said clock signal is in said first clock state.

Claim 53

Dependent Claim 90 words

The circuit of claim 43 wherein said master portion further comprises of: an input device for applying a charge state to a first node and maintaining a previous charge state on a second node in response to a first signal state when a clock signal is in a second clock state, said input device maintaining a previous charge state on said first node and applying a second charge state to said second node in response to a second signal state when said clock signal is in said second clock state.

Claim 54

Dependent Claim 28 words

The circuit of claim 43 wherein said master portion further comprises of: a control device for transmitting a signal in response to a charge state on a node.

Claim 55

Dependent Claim 48 words

The circuit of claim 50 wherein said control device is comprised of: a p channel transistor with a source coupled to a high voltage potential; and a n channel transistor with a source coupled to said p channel transistor and a drain coupled to a low voltage potential.

Claim 56

Dependent Claim 87 words

The circuit of claim 43 wherein said master portion further comprises of: a control device for transmitting a first signal state when a first node and a second node are both in a first charge state, said control device transmitting a second signal state when said first node and said second node are both in a second charge state, said output device maintaining a previous signal state when said first node is in said first charge state and said second node is in said second charge state.

Claim 57

Dependent Claim 41 words

The circuit of claim 43 wherein said slave portion further comprises of: a pass gate preventing signal to pass in response to a first clock state, said pass gate allowing said signal to pass in response to a second clock state.

Claim 58

Dependent Claim 50 words

The circuit of claim 53 wherein said pass gate is comprised of: a p channel transistor with a gate coupled to a first clock line; and a n channel transistor with a source and drain coupled to said p channel transistor and a gate coupled to a second clock line.

Claim 59

Dependent Claim 49 words

The circuit of claim 43 wherein said slave portion further comprises of: a first inverter coupled to a pass gate, said first inverter positioned in a first direction; and a second inverter coupled to said pass gate and said first inverter, said second inverter positioned in a second direction.

Claim 60

Dependent Claim 46 words

The circuit of claim 53 wherein said second inverter causes a third node to switch to a first voltage potential in response to a first signal state and causes said third node to switch to a second voltage potential in response to a second signal state.

Claim 61

Dependent Claim 95 words

The circuit of claim 53 wherein said first inverter comprises of a clocked inverter, said clocked inverter applying a first voltage potential to a fourth node in response to a second potential on a third node when a clock signal is in a first clock state, said clocked inverter applying a second voltage potential to a fourth node in response to a first potential on a third node when said clock signal is in said first clock state, said clocked inverter isolating a fourth node when said clock signal is in a second clock state.

Claim 62

Dependent Claim 117 words

The circuit of claim 57 wherein said clocked inverter is comprised of: a first p channel transistor with a source coupled to a high voltage potential; a second p channel transistor with a source coupled to said first p channel transistor and a gate coupled to a first clock line; a first n channel transistor with a drain coupled to a drain of said second p channel transistor and a gate coupled to a second clock line; and a second n channel transistor with a drain coupled to a source of said first n channel transistor, a source coupled to a low voltage potential and a gate coupled to a gate of said first p channel transistor.

Claim 63

Dependent Claim 52 words

The circuit of claim 55 wherein said first inverter and said second inverter further comprises of: a p channel transistor with a source coupled to a high voltage potential; and a n channel transistor with a drain coupled to said p channel transistor and a source coupled to a low voltage potential.

Claim 64

Dependent Claim 54 words

The circuit of claim 43 wherein said slave portion further comprises of: a third inverter coupled to a pass gate and coupled to an output line, said third inverter outputting a first signal state in response to a second signal state and outputting said second signal state in response to said first signal state.

Claim 65

Dependent Claim 22 words

The circuit of claim 43 wherein said circuit further comprises a delay circuit to delay a clock signal to said master portion.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-10-16	1999-04-17	1999-10-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-10-16	2003-04-17	2003-10-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-10-16	2007-04-17	2007-10-17	$7700.00	Window Closed / Lapsed

Dynamic-static master slave flip-flop circuit

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