Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array

Claim 2

A hierarchically-structured programmable logic array, comprising: a plurality of sectors, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system disposed externally to said sectors; and an interface for selectively coupling the plurality of sector bus systems to said block bus system, said interface having a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 3

The programmable logic array of claim 1, wherein said interface comprises: a multiplexer having a plurality of multiplexed ports coupled to at least one of said sector bus systems, and a de-multiplexed port; and a bi-directional driver having a first port coupled to said de-multiplexed port, and a second port selectively coupled to said block bus system.

Claim 4

The programmable logic array of claim 1, wherein at least one of said sectors comprises: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

Claim 5

A hierarchically-structured programmable logic array, comprising: a plurality of sectors arranged in rows and columns, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; at least one block row bus disposed between two rows of said sectors, and adjacent to each of the sectors in said two rows such that said block row bus is accessible to each of the sectors in said two rows, and at least one block column bus disposed between two columns of said sectors, and adjacent to each of the sectors in said two columns, such that said block column bus is accessible to each of the sectors in said two columns, said block row bus and said block column bus forming at least a portion of a block bus system; means for selectively coupling at least a portion of said block row bus to at least a portion of said block column bus; and an interface for selectively coupling the plurality of sector bus systems to said block bus system, said interface having a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 6

A hierarchically-structured programmable logic array, comprising: a plurality of sectors arranged in rows and columns, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; at least one block row bus disposed between two rows of said sectors, and adjacent to each of the sectors in said two rows such that said block row bus is accessible to each of the sectors in said two rows, and at least one block column bus disposed between two columns of said sectors, and adjacent to each of the sectors in said two columns, such that said block column bus is accessible to each of the sectors in said two columns, said block row bus and said block column bus forming at least a portion of a block bus system; means for selectively coupling at least a portion of said block row bus to at least a portion of said block column bus; and an interface for selectively coupling the plurality of sector bus systems to said block bus system, said interface having a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 7

The programmable logic array of claim 4, wherein said interface comprises: a multiplexer having a plurality of multiplexed ports coupled to at least one of said sector bus systems, and a de-multiplexed port; and a bi-directional driver having a first port coupled to said de-multiplexed port, and a second port selectively coupled to said block bus system.

Claim 8

The programmable logic array of claim 4, wherein at least one of said sectors comprises: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

Claim 9

A hierarchically-structured programmable logic array, comprising: a plurality of blocks; a chip bus system disposed external to said blocks; and a block interface for selectively coupling said blocks to said chip bus system; wherein at least one of said blocks comprises: a plurality of sectors arranged in rows and columns, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system, coupled selectively to said block interface, comprising: at least one block row bus, disposed between and external to two rows of said sectors, accessible to each of the sectors in said two rows; and at least one block column bus, disposed between and external to two columns of said sectors, accessible to each of the sectors in said two columns; means for coupling at least a portion of said block row bus to at least a portion of said block column bus; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 10

A hierarchically-structured programmable logic array, comprising: a plurality of blocks; a chip bus system disposed external to said blocks; and a block interface for selectively coupling said blocks to said chip bus system; wherein at least one of said blocks comprises: a plurality of sectors arranged in rows and columns, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system, coupled selectively to said block interface, comprising: at least one block row bus, disposed between and external to two rows of said sectors, accessible to each of the sectors in said two rows; and at least one block column bus, disposed between and external to two columns of said sectors, accessible to each of the sectors in said two columns; means for coupling at least a portion of said block row bus to at least a portion of said block column bus; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 11

The programmable logic array of claim 7, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 12

The programmable logic array of claim 7, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 13

The programmable logic array of claim 7, wherein at least one of said sectors comprises: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between and external to two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between and external to two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

Claim 14

The programmable logic array of claim 10, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 15

The programmable logic array of claim 10, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 16

A hierarchically-structured programmable logic array, comprising: a plurality of blocks; a chip bus system disposed external to said blocks; and a block interface for selectively coupling said blocks to said chip bus system; wherein at least one of said blocks comprises: a plurality of sectors, each sector comprising: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus; a block bus system disposed external to said sectors, said block bus system selectively coupled to said block interface; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 17

A hierarchically-structured programmable logic array, comprising: a plurality of blocks; a chip bus system disposed external to said blocks; and a block interface for selectively coupling said blocks to said chip bus system; wherein at least one of said blocks comprises: a plurality of sectors, each sector comprising: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus; a block bus system disposed external to said sectors, said block bus system selectively coupled to said block interface; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 18

The programmable logic array of claim 13, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 19

The programmable logic array of claim 13, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 20

An array of elements, comprising: a plurality of elements arranged in rows and columns; a plurality of non-segmented row busses, each disposed adjacent to at least one row of said elements, each row bus selectively coupled to an input and an output of each of the elements to which the row bus is adjacent; a plurality Of non-segmented column busses, each disposed adjacent to at least one column of said elements, each column bus selectively coupled to an input and an output of each of the elements to which the column bus is adjacent; and means for selectively coupling at least one of said row busses to at least one of said column busses; wherein the output of any of said elements may be coupled to the input of any of said elements using no more than one row bus, one column bus, and a single coupling between a row bus and a column bus; and wherein at least one of said elements comprises: a first, second, third and fourth multiplexers, each multiplexer having MUX input ports for receiving input signals, and a MUX output port for transmitting a MUX output signal; a first, second, third and fourth programmable inverters, each having an input port, an output port, and a control port, the input port of each of said programmable inverters coupled to the MUX output port of a corresponding one of said multiplexers, each of said programmable inverters responding to a control signal at its control port to provide at its output port an output signal which is either equivalent to the MUX output signal received at the input port, or is an inverted version of the MUX output signal received at the input port; a first NAND gate having inputs and an output the inputs of said first NAND gate coupled to the outputs of said first and second programmable inverters; a second NAND gate having inputs and an output, the inputs of said second NAND gate coupled to the outputs of said third and fourth programmable inverters; a first XOR gate having inputs and an output, the inputs of said first XOR gate coupled to the outputs of said first and second programmable inverters; a second XOR gate having inputs and an output, the inputs of said second XOR gate coupled to the outputs of said third and fourth programmable inverters; a first inverter having an input and an output, the input of said first inverter coupled to the output of said first NAND gate; a second inverter having an input and an output, the input of said second inverter coupled to the output of said second NAND gate; a fifth multiplexer having input ports and an output port, the input ports of said fifth multiplexer coupled to the outputs of said first NAND gate, said first XOR gate, and said first inverter; a sixth multiplexer having input ports and an output port, the input ports of said sixth multiplexer coupled to the outputs of said second NAND gate, said second XOR gate, and said second inverter; and a third NAND gate having inputs and an output, the inputs of said third NAND gate coupled to the outputs of said fifth and sixth multiplexers, the output of said third NAND gate representing an output of said element.

Claim 21

An array of elements, comprising: a plurality of elements arranged in rows and columns; a plurality of non-segmented row busses, each disposed adjacent to at least one row of said elements, each row bus selectively coupled to an input and an output of each of the elements to which the row bus is adjacent; a plurality Of non-segmented column busses, each disposed adjacent to at least one column of said elements, each column bus selectively coupled to an input and an output of each of the elements to which the column bus is adjacent; and means for selectively coupling at least one of said row busses to at least one of said column busses; wherein the output of any of said elements may be coupled to the input of any of said elements using no more than one row bus, one column bus, and a single coupling between a row bus and a column bus; and wherein at least one of said elements comprises: a first, second, third and fourth multiplexers, each multiplexer having MUX input ports for receiving input signals, and a MUX output port for transmitting a MUX output signal; a first, second, third and fourth programmable inverters, each having an input port, an output port, and a control port, the input port of each of said programmable inverters coupled to the MUX output port of a corresponding one of said multiplexers, each of said programmable inverters responding to a control signal at its control port to provide at its output port an output signal which is either equivalent to the MUX output signal received at the input port, or is an inverted version of the MUX output signal received at the input port; a first NAND gate having inputs and an output the inputs of said first NAND gate coupled to the outputs of said first and second programmable inverters; a second NAND gate having inputs and an output, the inputs of said second NAND gate coupled to the outputs of said third and fourth programmable inverters; a first XOR gate having inputs and an output, the inputs of said first XOR gate coupled to the outputs of said first and second programmable inverters; a second XOR gate having inputs and an output, the inputs of said second XOR gate coupled to the outputs of said third and fourth programmable inverters; a first inverter having an input and an output, the input of said first inverter coupled to the output of said first NAND gate; a second inverter having an input and an output, the input of said second inverter coupled to the output of said second NAND gate; a fifth multiplexer having input ports and an output port, the input ports of said fifth multiplexer coupled to the outputs of said first NAND gate, said first XOR gate, and said first inverter; a sixth multiplexer having input ports and an output port, the input ports of said sixth multiplexer coupled to the outputs of said second NAND gate, said second XOR gate, and said second inverter; and a third NAND gate having inputs and an output, the inputs of said third NAND gate coupled to the outputs of said fifth and sixth multiplexers, the output of said third NAND gate representing an output of said element.

Claim 22

A logic cell, comprising: a first, second, third and fourth multiplexers, each multiplexer having MUX input ports for receiving input signals, and a MUX output port for transmitting a MUX output signal; a first, second, third and fourth programmable inverters, each having an input port, an output port, and a control port, the input port of each of said programmable inverters coupled to the MUX output port of a corresponding one of said multiplexers, each of said programmable inverters responding to a control signal at its control port to provide at its output port an output signal which is either equivalent to the MUX output signal received at the input port, or is an inverted version of the MUX output signal received at the input port; a first NAND gate having inputs and an output, the inputs of said first NAND gate coupled to the outputs of said first and second programmable inverters; a second NAND gate having inputs and an output, the inputs of said second NAND gate coupled to the outputs of said third and fourth programmable inverters; a first XOR gate having inputs and an output, the inputs of said first XOR gate coupled to the outputs of said first and second programmable inverters; a second XOR gate having inputs and an output, the inputs of said second XOR gate coupled to the outputs of said third and fourth programmable inverters; a first inverter having an input and an output, the input of said first inverter coupled to the output of said first NAND gate; a second inverter having an input and an output, the input of said second inverter coupled to the output of said second NAND gate; a fifth multiplexer having input ports and an output port, the input ports of said fifth multiplexer coupled to the outputs of said first NAND gate, said first XOR gate, and said first inverter; a sixth multiplexer having input ports and an output port, the input ports of said sixth multiplexer coupled to the outputs of said second NAND gate, said second XOR gate, and said second inverter; and a third NAND gate having inputs and an output, the inputs of said third NAND gate coupled to the outputs of said fifth and sixth multiplexers the output of said third NAND gate representing an output of said logic cell.

Claim 23

A logic cell, comprising: a first, second, third and fourth multiplexers, each multiplexer having MUX input ports for receiving input signals, and a MUX output port for transmitting a MUX output signal; a first, second, third and fourth programmable inverters, each having an input port, an output port, and a control port, the input port of each of said programmable inverters coupled to the MUX output port of a corresponding one of said multiplexers, each of said programmable inverters responding to a control signal at its control port to provide at its output port an output signal which is either equivalent to the MUX output signal received at the input port, or is an inverted version of the MUX output signal received at the input port; a first NAND gate having inputs and an output, the inputs of said first NAND gate coupled to the outputs of said first and second programmable inverters; a second NAND gate having inputs and an output, the inputs of said second NAND gate coupled to the outputs of said third and fourth programmable inverters; a first XOR gate having inputs and an output, the inputs of said first XOR gate coupled to the outputs of said first and second programmable inverters; a second XOR gate having inputs and an output, the inputs of said second XOR gate coupled to the outputs of said third and fourth programmable inverters; a first inverter having an input and an output, the input of said first inverter coupled to the output of said first NAND gate; a second inverter having an input and an output, the input of said second inverter coupled to the output of said second NAND gate; a fifth multiplexer having input ports and an output port, the input ports of said fifth multiplexer coupled to the outputs of said first NAND gate, said first XOR gate, and said first inverter; a sixth multiplexer having input ports and an output port, the input ports of said sixth multiplexer coupled to the outputs of said second NAND gate, said second XOR gate, and said second inverter; and a third NAND gate having inputs and an output, the inputs of said third NAND gate coupled to the outputs of said fifth and sixth multiplexers the output of said third NAND gate representing an output of said logic cell.

Claim 24

The logic cell of claim 17, further comprising: a fifth programmable inverter having an input port, an output port, and a control port, the input port of said fifth programmable inverter coupled to the output of said third NAND gate, said fifth programmable inverter responding to a control signal at its control port to provide at its output port an output signal which is either equivalent to a signal received at its input port, or is an inverted version of the signal received at its input port.

Claim 25

A hierarchically-structured programmable logic array, comprising: a plurality of blocks arranged in rows and columns; a chip bus system comprising: at least one chip row bus, disposed between and external to two rows of said blocks, accessible to each of the blocks in said two rows; and at least one chip column bus, disposed between and external to two columns of said blocks, accessible to each of the blocks in said two columns; means for coupling at least a portion of said chip row bus to at least a portion of said chip column bus; and a block interface for selectively coupling said blocks to said chip bus system; wherein each of said blocks comprises: a plurality of sectors, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system disposed external to said sectors, said block bus system selectively coupled to said block interface; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 26

A hierarchically-structured programmable logic array, comprising: a plurality of blocks arranged in rows and columns; a chip bus system comprising: at least one chip row bus, disposed between and external to two rows of said blocks, accessible to each of the blocks in said two rows; and at least one chip column bus, disposed between and external to two columns of said blocks, accessible to each of the blocks in said two columns; means for coupling at least a portion of said chip row bus to at least a portion of said chip column bus; and a block interface for selectively coupling said blocks to said chip bus system; wherein each of said blocks comprises: a plurality of sectors, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system disposed external to said sectors, said block bus system selectively coupled to said block interface; and a sector interface for selectively coupling the plurality of sector bus systems to said block bus system.

Claim 27

The programmable logic array of claim 19, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 28

The programmable logic array of claim 19, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 29

The programmable logic array of claim 19, wherein at least one of said sectors comprises: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between and external to two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between and external to two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

Claim 30

The programmable logic array of claim 22, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 31

The programmable logic array of claim 22, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 32

The programmable logic array of claim 19, wherein at least one of said blocks comprises: a plurality of sectors arranged in rows and columns, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system, coupled selectively to said block interface, comprising: at least one block row bus, disposed between and external to two rows of said sectors, accessible to each of the sectors in said two rows; and at least one block column bus, disposed between and external to two columns of said sectors, accessible to each of the sectors in said two columns; and means for coupling at least a portion of said block row bus to at least a portion of said block column bus.

Claim 33

The programmable logic array of claim 25, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 34

The programmable logic array of claim 25, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.

Claim 35

The programmable logic array of claim 25, wherein at least one of said sectors comprises: a plurality of logic cells arranged in rows and columns; a sector bus system comprising: at least one sector row bus disposed between and external to two rows of said logic cells, and selectively coupled to the logic cells in said two rows; and at least one sector column bus disposed between and external to two columns of said logic cells, and selectively coupled to the logic cells in said two columns; and means for selectively coupling at least a portion of said sector row bus to at least a portion of said sector column bus.

Claim 36

The programmable logic array of claim 28, wherein said sector interface has a K number of lower level ports coupled to said sector bus systems, and an N number of higher level ports coupled to said block bus system, where N is less than K.

Claim 37

The programmable logic array of claim 28, wherein said block interface has a K number of lower level ports coupled to said block bus systems, and an N number of higher level ports coupled to said chip bus system, where N is less than K.