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US6115318A Expired / Lapsed US ⏱️ 0.0 years remaining

Clock vernier adjustment

Assignee: Round Rock Research LLC
•
Filing: 1996-12-03
•
Granted: 2000-09-05
•
Expires: 2016-12-03
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Abstract

Abstract A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.

Inventors

  • 👤 Brent Keeth

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 03:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/225; H; H03; H03K; H03K5/00; G11C7/10; G11C7/1051; G11C7/1078; G11C8/00; G11C8/06

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 106 words
An integrated circuit comprising: a vernier clock adjustment circuit receiving an input clock signal including a rising-edge delay circuit receiving the input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay, the vernier clock adjustment circuit further including a falling-edge delay circuit receiving the rising-edge clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 2
Dependent Claim 106 words
An integrated circuit comprising: a vernier clock adjustment circuit receiving an input clock signal including a rising-edge delay circuit receiving the input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay, the vernier clock adjustment circuit further including a falling-edge delay circuit receiving the rising-edge clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 3
Dependent Claim 105 words
An integrated circuit comprising: a vernier clock adjustment circuit receiving an input clock signal including a falling-edge delay circuit receiving the input clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; the vernier clock-adjustment circuit further including a rising-edge delay circuit receiving the falling-edge clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 4
Dependent Claim 105 words
An integrated circuit comprising: a vernier clock adjustment circuit receiving an input clock signal including a falling-edge delay circuit receiving the input clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; the vernier clock-adjustment circuit further including a rising-edge delay circuit receiving the falling-edge clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 5
Independent Claim 79 words
A method of operating in an integrated circuit comprising the steps of: receiving an input clock signal; delaying the input clock signal to provide a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; delaying the rising-edge clock signal to provide a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 6
Independent Claim 79 words
A method of operating in an integrated circuit comprising the steps of: receiving an input clock signal; delaying the input clock signal to provide a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; delaying the rising-edge clock signal to provide a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 7
Independent Claim 79 words
A method of operating in an integrated circuit comprising the steps of: receiving an input clock signal; delaying the input clock signal to provide a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; delaying the falling-edge clock signal to provide a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 8
Independent Claim 79 words
A method of operating in an integrated circuit comprising the steps of: receiving an input clock signal; delaying the input clock signal to provide a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; delaying the falling-edge clock signal to provide a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 9
Dependent Claim 184 words
A memory system comprising: a memory controller; a plurality of memory modules for storing data; a data bus for carrying write data from the memory controller to the plurality of memory modules and for carrying read data from the plurality of memory modules to the memory controller; a command bus carrying commands from the memory controller to the plurality of memory modules; a clock line for carrying an input clock signal from the memory controller to the plurality of memory modules; and wherein each memory module includes: a vernier clock adjustment circuit including a rising-edge delay circuit receiving the input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay, the vernier clock adjustment circuit further including a falling-edge delay circuit receiving the rising-edge clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 10
Dependent Claim 184 words
A memory system comprising: a memory controller; a plurality of memory modules for storing data; a data bus for carrying write data from the memory controller to the plurality of memory modules and for carrying read data from the plurality of memory modules to the memory controller; a command bus carrying commands from the memory controller to the plurality of memory modules; a clock line for carrying an input clock signal from the memory controller to the plurality of memory modules; and wherein each memory module includes: a vernier clock adjustment circuit including a rising-edge delay circuit receiving the input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay, the vernier clock adjustment circuit further including a falling-edge delay circuit receiving the rising-edge clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay; and an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 11
Dependent Claim 183 words
A memory system comprising: a memory controller: a plurality of memory modules for storing data; a data bus for carrying write data from the memory controller to the plurality of memory modules and for carrying read data from the plurality of memory modules to the memory controller; a command bus carrying commands from the memory controller to the plurality of memory modules; a clock line for carrying an input clock signal from the memory controller to the plurality of memory modules; and wherein each memory module includes: a vernier clock adjustment circuit including a falling-edge delay circuit receiving the input clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay, the vernier clock adjustment circuit further including a rising-edge delay circuit receiving the falling-edge clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.
Claim 12
Dependent Claim 183 words
A memory system comprising: a memory controller: a plurality of memory modules for storing data; a data bus for carrying write data from the memory controller to the plurality of memory modules and for carrying read data from the plurality of memory modules to the memory controller; a command bus carrying commands from the memory controller to the plurality of memory modules; a clock line for carrying an input clock signal from the memory controller to the plurality of memory modules; and wherein each memory module includes: a vernier clock adjustment circuit including a falling-edge delay circuit receiving the input clock signal and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay, the vernier clock adjustment circuit further including a rising-edge delay circuit receiving the falling-edge clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay; an edge triggered circuit receiving data and the rising-edge and falling-edge clock signals, and storing data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-09-05 2004-03-06 2004-09-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-09-05 2008-03-06 2008-09-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-09-05 2012-03-06 2012-09-05 $7700.00 Window Closed / Lapsed

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