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US5614855A Expired / Lapsed US ⏱️ 0.0 years remaining

Delay-locked loop

Assignee: Rambus Inc
•
Filing: 1995-08-21
•
Granted: 1997-03-25
•
Expires: 2015-08-21
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Abstract

Abstract A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90° ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

Inventors

  • 👤 Thomas H. Lee
  • 👤 Kevin S. Donnelly
  • 👤 Tsyr-Chyang Ho
  • 👤 Mark G. Johnson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 05:12
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 211 words
A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising: a duty cycle correcting amplifier coupled to receive the input signal, said amplifier correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal; a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase; a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; and a phase shifter coupled to receive the duty cycle corrected input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the duty cycle corrected input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector; wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.
Claim 2
Dependent Claim 211 words
A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising: a duty cycle correcting amplifier coupled to receive the input signal, said amplifier correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal; a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase; a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; and a phase shifter coupled to receive the duty cycle corrected input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the duty cycle corrected input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector; wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.
Claim 3
Dependent Claim 241 words
A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising: a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase; a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; a boost control signal coupled to the charge pump, said signal indicating when the circuit is in an acquisition mode wherein the circuit functions to acquire the desired timing relationship between the input signal and the output signal, said charge pump generating greater output current when said boost control signal is in a first state indicative that the circuit is in the acquisition mode; a phase shifter coupled to receive the input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector; wherein the jitter in the circuit is minimized by increasing the current output by the charge pump when the circuit is in the acquisition mode and maintaining the current output at a lower level when the circuit is not in the acquisition mode.
Claim 4
Dependent Claim 241 words
A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising: a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase; a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; a boost control signal coupled to the charge pump, said signal indicating when the circuit is in an acquisition mode wherein the circuit functions to acquire the desired timing relationship between the input signal and the output signal, said charge pump generating greater output current when said boost control signal is in a first state indicative that the circuit is in the acquisition mode; a phase shifter coupled to receive the input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector; wherein the jitter in the circuit is minimized by increasing the current output by the charge pump when the circuit is in the acquisition mode and maintaining the current output at a lower level when the circuit is not in the acquisition mode.
Claim 5
Independent Claim 136 words
A method for generating an output signal having a predetermined timing relationship with an input signal, said method comprising the steps of: correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal; generating a phase output signal indicative of whether the output signal is ahead or behind the input signal in phase; generating a current; and performing a phase shift of the duty cycle corrected input signal to produce the output signal, said step driven by the current, said direction of the phase shift indicated by the phase detector; wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.
Claim 6
Independent Claim 136 words
A method for generating an output signal having a predetermined timing relationship with an input signal, said method comprising the steps of: correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal; generating a phase output signal indicative of whether the output signal is ahead or behind the input signal in phase; generating a current; and performing a phase shift of the duty cycle corrected input signal to produce the output signal, said step driven by the current, said direction of the phase shift indicated by the phase detector; wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.

References Cited (Backward Citations)

US3296517A Cited
US3546604A Cited
US3555458A Cited
US3675139A Cited
US3617855A Cited
US3771063A Cited
US3825768A Cited
US3863080A Cited
US3911368A Cited
US4021742A Cited
US3965433A Cited
US3982190A Cited
US3997772A Cited
US4178554A Cited
US4110641A Cited
US4285006A Cited
US4156851A Cited
US4151463A Cited
US4291274A Cited
US4249095A Cited
US4283682A Cited
US4364082A Cited
US4473762A Cited
US4383216A Cited
US4373204A Cited
US4394587A Cited
US4468689A Cited
US4520321A Cited
US4924117A Cited
US4506175A Cited
US4494021A Cited
US4789799A Cited
GB2140993B Cited
US4547685A Cited
US4573022A Cited
US4607229A Cited
US4719365A Cited
US4635097A Cited
US4641048A Cited
US4623805A Cited
US4721904A Cited
US4644196A Cited
US4739279A Cited
US4724337A Cited
US4638190A Cited
US4785206A Cited
US4746819A Cited
US4931675A Cited
US4806888A Cited
US4691124A Cited
US4751469A Cited
US4868512A Cited
US4815113A Cited
US4739194A Cited
US4904948A Cited
US4813005A Cited
US4818901A Cited
US4935701A Cited
US4814648A Cited
US4845675A Cited
US4929916A Cited
US4866397A Cited
US5120954A Cited
US4870303A Cited
US4937476A Cited
US4963817A Cited
US5015872A Cited
US4973864A Cited
US4992757A Cited
EP0407591B1 Cited
US4994773A Cited
US5126854A Cited
US5253187A Cited
US4893094A Cited
US5123020A Cited
US5132640A Cited
US5057788A Cited
US4958133A Cited
US5077489A Cited
US5164838A Cited
US5220294A Cited
US5281865A Cited
US5148113A Cited
US5248946A Cited
US5253042A Cited
US5223755A Cited
US5128554A Cited
US5121010A Cited
US5095233A Cited
US5079519A Cited
US5132567A Cited
US5175879A Cited
US5223753A Cited
US5182476A Cited
US5126693A Cited
US5157276A Cited
US5179303A Cited
US5440274A Cited
US5309162A Cited
US5448200A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-03-24 2000-09-23 2001-03-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-03-24 2004-09-23 2005-03-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-03-24 2008-09-23 2009-03-25 $7700.00 Window Closed / Lapsed

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