High-speed data latch with zero data hold time

Claim 2

A data latch circuit, comprising: an input data storage section for receiving data input to said data latch circuit; an output data storage section prechargeable to a predetermined state; a transfer circuit operative during a transfer cycle for transferring data from said input data storage section to said output data storage section; an output for outputting data from said data latch circuit; and an inhibit circuit for allowing a transfer of data from said input storage section to said output storage section to change an initial precharged state thereof, but preventing a subsequent transfer of data until said output storage section is again precharged.

Claim 3

The data latch circuit of claim 1, wherein said inhibit circuit is cross-coupled between said input data storage section and said output data storage section.

Claim 4

The data latch circuit of claim 2, wherein said input and output data storage sections each comprise a flip-flop, and said inhibit circuit comprises a first transistor cross-coupled between said input and output data storage sections, a second transistor cross-coupled between said input and output data storage sections, said first and second transistors being responsive to a data state transferred to said data output section for preventing a change in said data state as a result of a change in a data state input to said input data storage section.

Claim 5

The data latch circuit of claim 3, further including a clock driver for alternately precharging said data latch circuit during one cycle and for inputting data to said data latch circuit during another cycle.

Claim 6

A data latch circuit, comprising: an input flip-flop for inputting data into said data latch circuit, said input flip-flop having a pair of output nodes; an output flip-flop for providing a pair of output nodes of said data latch circuit; a precharge circuit for precharging said output nodes to a predetermined state; a pair of transistors, each operative for transferring data between respective said nodes of said input and output flip-flops; a first pair of series-connected transistors connected between one said node of said input flip-flop and a reference voltage, a first transistor of said first pair being driven by an input data signal and a second transistor of said pair being cross-coupled to an output node of said output flip-flop; and a second pair of series-connected transistors connected between a different node of said input flip-flop and a reference voltage, a first transistor of said second pair being driven by a complement of said input data signal and a second transistor of said second pair being cross-coupled to a different output node of said output flip-flop.

Claim 7

A data latch circuit, comprising: an input flip-flop for inputting data into said data latch circuit, said input flip-flop having a pair of output nodes; an output flip-flop for providing a pair of output nodes of said data latch circuit; a precharge circuit for precharging said output nodes to a predetermined state; a pair of transistors, each operative for transferring data between respective said nodes of said input and output flip-flops; a first pair of series-connected transistors connected between one said node of said input flip-flop and a reference voltage, a first transistor of said first pair being driven by an input data signal and a second transistor of said pair being cross-coupled to an output node of said output flip-flop; and a second pair of series-connected transistors connected between a different node of said input flip-flop and a reference voltage, a first transistor of said second pair being driven by a complement of said input data signal and a second transistor of said second pair being cross-coupled to a different output node of said output flip-flop.

Claim 8

The data latch circuit of claim 5, wherein said input flip-flop comprises N-channel transistors and said output flip-flop comprises P-channel transistors, and wherein said precharged circuit comprises P-channel transistors, and said transfer transistors and said first and second pair of transistors comprise N-channel transistors.

Claim 9

The data latch circuit of claim 5, further including a clock driver for alternately precharging said data latch circuit during one clock cycle and for inputting data to said data latch circuit during another clock cycle.

Claim 10

A data latch circuit, comprising: an input flip-flop for inputting data into said latch circuit, said input flip-flop having a pair of output nodes; an output flip-flop for providing a pair of output nodes of said data latch circuit; a precharge circuit for precharging said output nodes of said output flip-flop to a predetermined state; a pair of transistors, each operative for transferring data between respective said nodes of said input and output flip-flops; a data input circuit for inputting a data signal and a complement of said data signal to said input flip-flop; and an inhibit circuit for providing feedback of data set into said output flip-flop back to said data input circuit to prevent a subsequent change in the data signal from changing the state of the output flip-flop.

Claim 11

A data latch circuit, comprising: an input flip-flop for inputting data into said latch circuit, said input flip-flop having a pair of output nodes; an output flip-flop for providing a pair of output nodes of said data latch circuit; a precharge circuit for precharging said output nodes of said output flip-flop to a predetermined state; a pair of transistors, each operative for transferring data between respective said nodes of said input and output flip-flops; a data input circuit for inputting a data signal and a complement of said data signal to said input flip-flop; and an inhibit circuit for providing feedback of data set into said output flip-flop back to said data input circuit to prevent a subsequent change in the data signal from changing the state of the output flip-flop.

Claim 12

The data latch circuit of claim 8, wherein said data input circuit includes a first transistor responsive to data input to said input flip-flop, and said inhibit circuit comprises a second transistor in series with said first transistor, said second transistor being cross-coupled to an output node of said output flip-flop.

Claim 13

The data latch circuit of claim 9, wherein said first and second transistors are arranged so that an initial data signal input to said input flip-flop is transferred to said output flip-flop, said first and second transistors being in an identical state, and when the data signal changes one said transistor is driven to a different state so that at least one of said first or second transistors interrupts a positive feedback between said input and output flip-flop and said latch is prevented from changing state.

Claim 14

The data latch circuit of claim 8, further including in combination an analog to digital converter encapsulated to form an integrated circuit.

Claim 15

The data latch circuit of claim 8, further including in combination a digital to analog converter encapsulated to form an integrated circuit.

Claim 16

The data latch circuit if claim 8, further including in combination a memory encapsulated to form an integrated circuit.

Claim 17

A high-speed sense amplifier for use with a memory of the type having prechargeable complementary bit lines, comprising: an output flip-flop having a pair of prechargeable output nodes providing an output of said sense amplifier; an input flip-flop having a pair of inputs connected respectively to said complementary bit lines, and a pair of output nodes; a pair transfer transistors each operative for transferring data from the output nodes of said input flip-flop to the precharged output nodes of said output flip-flop; a clock signal generator having two alternating states, one state for precharging said bit lines and one state for reading said memory; a precharge circuit for precharging the output nodes of said output flip-flop during the memory read state in which data is read from a cell of said memory onto said complementary bit lines; and an inhibit circuit responsive to the slewing of said output flip-flop to a definable state for inhibiting a change of state thereof as a result of a change of signal states on said bit lines.

Claim 18

A high-speed sense amplifier for use with a memory of the type having prechargeable complementary bit lines, comprising: an output flip-flop having a pair of prechargeable output nodes providing an output of said sense amplifier; an input flip-flop having a pair of inputs connected respectively to said complementary bit lines, and a pair of output nodes; a pair transfer transistors each operative for transferring data from the output nodes of said input flip-flop to the precharged output nodes of said output flip-flop; a clock signal generator having two alternating states, one state for precharging said bit lines and one state for reading said memory; a precharge circuit for precharging the output nodes of said output flip-flop during the memory read state in which data is read from a cell of said memory onto said complementary bit lines; and an inhibit circuit responsive to the slewing of said output flip-flop to a definable state for inhibiting a change of state thereof as a result of a change of signal states on said bit lines.

Claim 19

The sense amplifier of claim 14, wherein said output flip-flop is responsive to a transition of said clock signal for slewing toward a definable state as established in said input flip-flop, and said inhibit circuit is responsive to said output flip-flop slewing for inhibiting a change of state of said output flip-flop.

Claim 20

The sense amplifier of claim 14, wherein said output flip-flop nodes are precharged during the same clock signal state which also reads said memory.

Claim 21

The sense amplifier of claim 14, wherein said bit lines are precharged during the same state of said clock signal in which data is input to said sense amplifier.

Claim 22

The sense amplifier of claim 17, wherein said bit line precharging occurs substantially from one transition of said clock signal to a subsequent clock signal transition.

Claim 23

The sense amplifier of claim 14, wherein said sense amplifier is effective to latch data therein during a transition of said clock signal, and begin precharging said bit lines during the same clock signal transition.

Claim 24

The sense amplifier of claim 14, further including a bit line precharge circuit for precharging said bit lines in response to a clock signal which is coupled to said output flip-flop for precharging the output nodes thereof.

Claim 27

The method of claim 21, further including latching data in said sense amplifier during an initial portion of said transition and beginning said bit line precharging during a subsequent portion of said transition.

Claim 28

The method of claim 21, further including controlling all operations of said sense amplifier with a single clock signal.

Claim 29

The method of claim 23, further including precharging the sense amplifier circuits during a first state of said clock signal and inputting data thereto during a different clock signal state.

Claim 30

The method of claim 21, further including performing a read operation of said memory in which data is output therefrom in a single cycle of said clock signal.

Claim 33

The method of claim 26, further including constructing said latch as a balanced circuit having a pair of prechargeable nodes which slew toward different states, and a pair of complementary data inputs.

Claim 34

The method of claim 27, further including disconnecting each said data input after said slewing and in response to a change of input data.

Claim 35

The method of claim 26, further including constructing said latch with a data output section connected to a data input section with a feedback path therebetween, providing feedback on said path when a definable state of said output section coincides with a data state input to said input section, and disconnecting said feedback path when said definable state differs from said data state input to said input section.

Claim 36

The method of claim 29, further including constructing said feedback path with a pair of series-connected transistors with inputs connected respectively to said output section and to an input of said input section.

Claim 37

The method of claim 26, further including fabricating said latch in an integrated circuit with an analog to digital converter.

Claim 38

The method of claim 26, further including fabricating said latch in an integrated circuit with a digital to analog converter.

Claim 39

The method of claim 26, further including fabricating said latch in an integrated circuit with a semiconductor memory.