US5126854A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase lock circuit for generating a phase synched synchronizing video signal
Assignee: Fujitsu Ltd
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Filing: 1989-10-24
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Granted: 1992-06-30
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Expires: 2009-10-24
Abstract
Abstract A phase lock circuit includes a control signal generator which generates a control signal changing for every frame consisting of an odd-numbered field and an even-numbered field in a reproduction mode. The control signal has a first level for a frame and a second level for a subsequent frame. The phase lock circuit further includes a first PLL circuit and a second PLL circuit. The first PLL circuit generates a first synchronizing signal which is phase-locked with a reproduced synchronizing signal for every other frame when the control signal is at the first level. The second PLL circuit generates a second synchronizing signal which is phase-locked with the reproduced synchronizing signal for every other frame when the control signal is at the second level. Furthermore, the phase lock circuit includes a select circuit which selects one of the first and second synchronizing signals supplied from the first and second PLL circuits on the basis of the control signal. The selected synchronizing signal is the synchronizing signal output from the phase lock circuit.
Inventors
- 👤 Shoichi Sano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:13
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/9305; H04N5/932
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
239 words
A phase lock circuit for generating a synchronizing signal output which is phase with a synchronizing signal reproduced from a video disc player, said video disc player having a reproduction mode in which said reproduced synchronizing signal is generated for each frame comprising both an odd-numbered field and an even-numbered field, said phase lock circuit comprising: control signal generating means for generating a control signal, said control signal having a first level for a first frame and a second level for a second frame, the first and second levels of said control signal changing for said first and second frames; first phase locked loop means, coupled to said control signal generating means, for generating a first synchronizing signal which is phase-locked with said reproduced synchronizing signal for every other frame when said control signal is at said first level; second phase locked loop means, coupled to said control signal generating means, for generating a second synchronizing signal which is phase-locked with said reproduced synchronizing signal for every other frame when said control signal is at said second level; and selecting means, coupled to said control signal generating means and said first and second phase locked loop means, for selecting one of said first and second synchronizing signals respectively generated by said first and second phase locked loop means on the basis f said control signal, the selected synchronizing signal being said synchronizing signal output of said phase lock circuit.
Claim 2
Dependent Claim
239 words
A phase lock circuit for generating a synchronizing signal output which is phase with a synchronizing signal reproduced from a video disc player, said video disc player having a reproduction mode in which said reproduced synchronizing signal is generated for each frame comprising both an odd-numbered field and an even-numbered field, said phase lock circuit comprising: control signal generating means for generating a control signal, said control signal having a first level for a first frame and a second level for a second frame, the first and second levels of said control signal changing for said first and second frames; first phase locked loop means, coupled to said control signal generating means, for generating a first synchronizing signal which is phase-locked with said reproduced synchronizing signal for every other frame when said control signal is at said first level; second phase locked loop means, coupled to said control signal generating means, for generating a second synchronizing signal which is phase-locked with said reproduced synchronizing signal for every other frame when said control signal is at said second level; and selecting means, coupled to said control signal generating means and said first and second phase locked loop means, for selecting one of said first and second synchronizing signals respectively generated by said first and second phase locked loop means on the basis f said control signal, the selected synchronizing signal being said synchronizing signal output of said phase lock circuit.
Claim 3
Dependent Claim
138 words
A phase lock circuit as claimed in claim 1, wherein said first phase locked loop means includes voltage controlled oscillator means for generating a system clock, frequency dividing means for frequency-dividing said system clock and thereby generating said first synchronizing signal, phase comparing means for comparing the phase of said first synchronizing signal with said reproduced synchronizing signal and thereby generating an error signal, and selective holding means for selectively passing said error signal supplied from said phase comparing means when said control signal is at said first level and for holding said error signal when said control signal is at said second level, said error signal supplied from said selective holding means being supplied to said voltage controlled oscillator means and said voltage controlled oscillator means being controlled by said error signal in generating said system clock.
Claim 4
Dependent Claim
27 words
A phase lock circuit as claimed in claim 2, wherein when said control signal is at said first level, said selecting means selects said first synchronizing signal.
Claim 5
Dependent Claim
20 words
A phase lock circuit as claimed in claim 2, wherein the frequency of said system clock is equal to 23MHz.
Claim 6
Dependent Claim
132 words
A phase lock circuit as claimed in claim 1, wherein said second phase locked loop means includes voltage controlled oscillator means for generating a system clock, frequency dividing means for frequency-dividing said system clock and thereby generating said second synchronizing signal, phase comparing means for comparing the phase of said second synchronizing signal with said reproduced synchronizing signal and thereby generating an error signal, and selective holding means for selectively passing said error signal supplied from said phase comparing means when said control signal is at said second level and for holding said error signal when said control signal is at said first level, said error signal supplied from said selective holding means being supplied to said voltage controlled oscillator means being controlled by said error signal in generating said system clock.
Claim 7
Dependent Claim
27 words
A phase lock circuit as claimed in claim 5, wherein when said control signal is at said second level, said selecting means selects said second synchronizing signal.
Claim 8
Dependent Claim
143 words
A phase lock circuit as claimed in claim 1, wherein said reproduced synchronizing signal includes a horizontal synchronizing signal and a vertical synchronizing signal, and said control signal generating means includes discriminating means for receiving said horizontal and vertical synchronizing signals, and in response thereto for discriminating said odd-numbered field of said reproduced synchronizing signal from said evennumbered field thereof and for generating a decision signal having a first decision level for said odd-numbered field and a second decision level for said even-numbered field, and frequency dividing means for dividing a first frequency of said decision signal into a signal having a second frequency equal to half the first frequency of said decision signal, and wherein said signal supplied from said frequency dividing means is supplied, as said control signal, to said first and second phase locked loop means and said selecting means.
Claim 9
Dependent Claim
18 words
A phase lock circuit as claimed in claim 1, wherein said synchronizing signal is a horizontal synchronizing signal.
Claim 10
Dependent Claim
20 words
A phase lock circuit as claimed in claim 1, wherein the frequency of said synchronizing signal is equal to 15.75kHz.
Claim 11
Dependent Claim
21 words
A phase lock circuit as claimed in claim 1, wherein said synchronizing signal is in conformity with the IEA RS-170A standard.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |