Method and circuit arrangement for generating a phase shifted clock pulse signal

Claim 3

A method as in claim 1, wherein said steps of dividing the frequency of the original signal in half and generating phase shifts of the frequency-halved signal at 0, -π/2 and -π are performed with a master-slave D-flip-flop cascade having a master and a slave, the cascade being supplemented by an inverted feedback to form a ring, the steps of generating the first and second variable phase shifted signals including the steps of applying output signals of both the slave and the master to input ports of the first phase shifter and to input ports of the second phase shifter.

Claim 4

A method as defined in claim 1, wherein said step of doubling the frequency is performed with an exclusive OR member having two input ports and wherein said step of doubling comprises the step of feeding the two input ports of the exclusive OR member with output signals of the first and second phase shifters.

Claim 5

A method as in claim 3, further comprising the step of additionally generating the output signal of the exclusive OR member in inverted form.

Claim 6

A method as in claim 14 further comprising the step of amplifying the low pass filtered signals.

Claim 7

A circuit for generating a phase shifted clock pulse signal, comprising: a frequency divider having a clock pulse input for receiving a signal to be phase shifted, including a master-slave D-flip flop having a master and a slave, an inverted feedback from the slave to the master forming a ring, one of the master and slave having first and second master-slave output signals whose frequency is equal to halve of the frequency of the clock pulse input and whose phases are respectively shifted by 0 and -π, and the other of the master and slave having a third master-slave output signal whose frequency is equal to halve of the frequency of the clock pulse input and a phase shifted by -π/2; first and second phase shifters jointly controlled by a single control signal, said first phase shifter having first and second input ports respectively coupled to the first and third master-slave output signals, said second phase shifter having third and fourth input ports respectively coupled to the second and third master-slave output signals, said first phase shifter being responsive to the control signal for adjusting the phase of a first phase shifter output signal to any value between the respective phases of the first and third master-slave output signals, depending on the value of the control signal, said second phase shifter being responsive to the control signal for adjusting the phase of a second phase shifter output signal to any value between the respective phases of the second and third master-slave output signals, depending on the value of the control signal; and a first exclusive or member having input ports respectively coupled to output ports of said first and second phase shifters so as to receive the first and second phase shifter output signals and provide an output signal which has a phase which is shifted by a desired value depending on the value of the control signal, in the range zero to -π with reference to the phase of the clock pulse input.

Claim 8

A circuit for generating a phase shifted clock pulse signal, comprising: a frequency divider having a clock pulse input for receiving a signal to be phase shifted, including a master-slave D-flip flop having a master and a slave, an inverted feedback from the slave to the master forming a ring, one of the master and slave having first and second master-slave output signals whose frequency is equal to halve of the frequency of the clock pulse input and whose phases are respectively shifted by 0 and -π, and the other of the master and slave having a third master-slave output signal whose frequency is equal to halve of the frequency of the clock pulse input and a phase shifted by -π/2; first and second phase shifters jointly controlled by a single control signal, said first phase shifter having first and second input ports respectively coupled to the first and third master-slave output signals, said second phase shifter having third and fourth input ports respectively coupled to the second and third master-slave output signals, said first phase shifter being responsive to the control signal for adjusting the phase of a first phase shifter output signal to any value between the respective phases of the first and third master-slave output signals, depending on the value of the control signal, said second phase shifter being responsive to the control signal for adjusting the phase of a second phase shifter output signal to any value between the respective phases of the second and third master-slave output signals, depending on the value of the control signal; and a first exclusive or member having input ports respectively coupled to output ports of said first and second phase shifters so as to receive the first and second phase shifter output signals and provide an output signal which has a phase which is shifted by a desired value depending on the value of the control signal, in the range zero to -π with reference to the phase of the clock pulse input.

Claim 9

A circuit as in claim 6, further comprising a buffer amplifier connected to an output port of said first exclusive OR member.

Claim 10

A circuit as in claim 6, further comprising first and second amplifiers respectively coupling the output ports of said first and second phase shifters to the input ports of said first exclusive OR member.

Claim 11

A circuit as in claim 6, wherein said first exclusive OR member has an inverting output port for outputting a signal which has a phase which is shifted by a desired value depending on the value of the control signal, in the range -π to -2π with reference to the phase of the clock pulse input.

Claim 12

A circuit as in claim 7, wherein said buffer amplifier has an inverting output port and a noninverting output port.

Claim 13

A circuit as in claim 6, further comprising a second exclusive OR member coupled at one input port thereof to an output port of said first exclusive OR member, whereby by application of a binary signal to a second input port of said second exclusive OR member, the phase of the output port of said second exclusive OR member is switchable between a phase range from 0 to -π and a phase range from -π to -2π.

Claim 14

A circuit as in claim 6, wherein said first and second phase shifters each include a temperature compensation circuit connected to an input port for the common control signal so to provide a temperature coefficient for each of said first and second phase shifters.

Claim 15

An apparatus as in claim 15, further comprising amplifiers connected to output ports of said lowpass filter means.

Claim 16

A method as in claim 1, further comprising lowpass filtering at least one of the output and input signals of the first and second controllable phase shifters so as to attenuate in amplitude any existing harmonics with respect to the frequency-halved signal.

Claim 17

A circuit as in claim 6, further comprising lowpass filter means coupled to the input ports or the output ports or both the input and the output ports, of said first and second phase shifters, for lowpass filtering the first, second and third master/slave output signals and/or the first and second phase shifter output signals, so as to attenuate the amplitude of harmonics of the first, second and third master/slave output signals and/or of the first and second phase shifter output signals.