US5248946A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetrical differential amplifier circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1991-12-11
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Granted: 1993-09-28
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Expires: 2011-12-11
Abstract
Abstract An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions. Furthermore, an offset voltage caused in each amplifier circuit is canceled out by connecting two sets of symmetrical-type amplifier circuits.
Inventors
- 👤 Shuji Murakami
- 👤 Atsushi Ohba
- 👤 Kenji Anami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:34
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
289 words
An amplifier circuit for amplifying the potential difference between first and second input signals, comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals for receiving said first and second input signals, respectively, at the gates; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said first input transistor; and third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; the conductance of said first input transistor and the conductance of said second input transistor being selected to be equal; the conductance of said second load transistor and the conductance of said third load transistor being selected to be respectively larger than the conductance of said first load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor; and output signals being obtained from said first conducting terminals of said first and second input transistors.
Claim 2
Dependent Claim
289 words
An amplifier circuit for amplifying the potential difference between first and second input signals, comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals for receiving said first and second input signals, respectively, at the gates; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said first input transistor; and third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; the conductance of said first input transistor and the conductance of said second input transistor being selected to be equal; the conductance of said second load transistor and the conductance of said third load transistor being selected to be respectively larger than the conductance of said first load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor; and output signals being obtained from said first conducting terminals of said first and second input transistors.
Claim 3
Dependent Claim
27 words
The amplifier circuit according to claim 1, further comprising a transistor for current control connected to said second conducting terminals of said first and second input transistors.
Claim 4
Dependent Claim
27 words
The amplifier circuit according to claim 1, further comprising a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
Claim 5
Dependent Claim
315 words
An amplifier circuit for amplifying a potential difference between first and second input signals, comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals for receiving said first and second input signals, respectively, at the gates; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said first input transistor; and third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; said gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; the ratio of the conductance of said first input transistor to the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the ratio of the conductance of said second input transistor to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor, the conductance of said second load transistor, and the conductance of said first input transistor being selected to be a value different from the value of the sum of the conductance of said first load transistor, the conductance of said fourth load transistor, and the conductance of said second input transistor; and output signals being obtained from said first conducting terminals of said first and second input transistors.
Claim 6
Dependent Claim
315 words
An amplifier circuit for amplifying a potential difference between first and second input signals, comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals for receiving said first and second input signals, respectively, at the gates; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said first input transistor; and third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; said gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; the ratio of the conductance of said first input transistor to the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the ratio of the conductance of said second input transistor to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor, the conductance of said second load transistor, and the conductance of said first input transistor being selected to be a value different from the value of the sum of the conductance of said first load transistor, the conductance of said fourth load transistor, and the conductance of said second input transistor; and output signals being obtained from said first conducting terminals of said first and second input transistors.
Claim 7
Dependent Claim
27 words
The amplifier circuit according to claim 4, further comprising a transistor for current control connected to said second conducting terminals of said first and second input transistors.
Claim 8
Dependent Claim
27 words
The amplifier circuit according to claim 4, further comprising a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
Claim 9
Dependent Claim
284 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
Claim 10
Dependent Claim
284 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
Claim 11
Dependent Claim
356 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein the conductance of said first input transistor and the conductance of said second input transistor being selected to be equal; the conductance of said second load transistor and the conductance of said third load transistor being selected to be respectively larger than the conductance of said first load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor.
Claim 12
Dependent Claim
356 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein the conductance of said first input transistor and the conductance of said second input transistor being selected to be equal; the conductance of said second load transistor and the conductance of said third load transistor being selected to be respectively larger than the conductance of said first load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor and the conductance of said second load transistor being selected to be equal to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor.
Claim 13
Dependent Claim
36 words
The amplifier circuit according to claim 8, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first and second input transistors.
Claim 14
Dependent Claim
36 words
The amplifier circuit according to claim 8, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
Claim 15
Dependent Claim
382 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein the ratio of the conductance of said first input transistor to the sum of the conductance of said first load transistor and the conductance of said second load transistor is selected to be equal to the ratio of the conductance of said second input transistor to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor, the conductance of said second load transistor, and the conductance of said first input transistor is selected to be a value different from the value of the sum of the conductance of said third load transistor, the conductance of said fourth load transistor, and the conductance of said second input transistor.
Claim 16
Dependent Claim
382 words
An amplifier circuit for amplifying a potential difference between first and second input signals comprising first and second amplifying means connected in a differential manner, said first and second amplifying means each comprising: first and second input transistors of a first conductivity type each having a gate and first and second conducting terminals; first and second load transistors of a second conductivity type each having a gate and first and second conducting terminals and having said conducting terminal connected to said first conducting terminal of said first input transistor; third and fourth load transistors of the second conductivity type each having a gate and first and second conducting terminals and having said first conducting terminal connected to said first conducting terminal of said second input transistor; the gates of said first and third load transistors being connected to each other and to said first conducting terminal of said first input transistor; the gates of said second and fourth load transistors being connected to each other and to said first conducting terminal of said second input transistor; said first input signal being applied to the gate of said first input transistor in said first amplifying means and to the gate of said second input transistor in said second amplifying means; and output signals being obtained from said first conducting terminal of one of said first and second input transistors in said first amplifying means and from said first conducting terminal of the other one of said first and second input transistors in said second amplifying means, wherein the ratio of the conductance of said first input transistor to the sum of the conductance of said first load transistor and the conductance of said second load transistor is selected to be equal to the ratio of the conductance of said second input transistor to the sum of the conductance of said third load transistor and the conductance of said fourth load transistor, and the sum of the conductance of said first load transistor, the conductance of said second load transistor, and the conductance of said first input transistor is selected to be a value different from the value of the sum of the conductance of said third load transistor, the conductance of said fourth load transistor, and the conductance of said second input transistor.
Claim 17
Dependent Claim
36 words
The amplifier circuit according to claim 11, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first and second input transistors.
Claim 18
Dependent Claim
36 words
The amplifier circuit according to claim 14, wherein each of said first and second amplifying means further includes a transistor for current control connected to said second conducting terminals of said first to fourth load transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-27 | 2005-03-29 | 2005-09-28 | $7700.00 | Window Closed / Lapsed |