CMOS Sense amplifier

Claim 1

A memory circuit comprising: (a) a plurality of memory cells arranged in rows and columns; (b) a plurality of word lines each being connected to ones of said memory cells in a different row and being used for selecting said memory cells in that row; (c) a plurality of pairs of digit lines, each of said pairs being connected to ones of said memory cells in a different column of memory cells such that when a memory cell is selected by one of said word lines, the output of said selected memory cell appears across the pair of digit lines connected to said selected memory cell; (d) a plurality of column lines each corresponding to a different one of said digit line pairs; (e) a plurality of sense preamplifiers, each of said sense preamplifiers being coupled to a different one of said plurality of digit line pairs and being activated by a column line corresponding to the digit line pair coupled to the preamplifier, each of said sense preamplifiers including first and second MOS input transistors of a first channel type each having a gate, drain and source, said sources of said input transistors being connected together and said gates of said input transistors being connected to a different one of the digit lines in the digit line pair coupled to the preamplifier, and first and second MOS switching transistors of said first channel type, each of said switching transistors having a gate, drain and source, said sources of said switching transistors being connected respectively to said drains of said first and second input MOS transistors and said gates of said switching MOS transistors being connected to the column line corresponding to said coupled digit line pair; (f) a load circuit connected to each of said plurality of sense preamplifiers, said load circuit including first and second load MOS transistors of a second channel type each having a gate, drain and source, and drains of said first and second load MOS transistors being connected to said drains of said first switching MOS transistors in each of said sense preamplifiers and said gates of said first and second load MOS transistors being connected respectively to said drains of said first and second switching MOS transistors in each of said sense preamplifiers, and third and fourth load MOS transistors of said second channel type each having a gate, drain and source, said drains of said third and fourth load MOS transistors being connected to said drains of said second switching MOS transistors in each of said sense preamplifiers and said gates of said third and fourth load MOS transistors being connected respectively to said drains of said first and second switching MOS transistors in each of said sense preamplifiers; and (g) a differential amplifier having one input connected to said gates of said first and third load MOS transistors in said load circuit and another input connected to said gates of said second and fourth transistors, the output of said differential amplifier indicating the contents of a memory cell selected by a work line and coupled, through a digit line pair, to a sense preamplifier selected by a column line.