Semiconductor memory device

Abstract

Abstract In a semiconductor memory device having a sense amplifier (22) for amplifying a potential difference between a pair of regular bit lines (11, 11 ), the memory device further comprises a dummy bit line (41) having a load capacitance equal to that of each of the pair of regular bit lines, a dummy memory cell (42) having a bit line drive capability equal to that of the regular memory cell (14), a precharging circuit (43) for precharging the dummy bit line, a selecting circuit for simultaneously selecting the regular memory cell and the dummy memory cell, a dummy bit line potential sensing circuit (50) for sensing that the potential of the dummy bit line is changed from a precharge potential by a predetermined potential when the dummy memory cell is selected by the selecting circuit, and a sense amplifier control circuit (51, 49, 52) for receiving an enable signal which enables operation of the sense amplifier, and a sensed signal from the dummy bit line potential sensing circuit, to determine an operation period of the sense amplifier, in response to both the enable and the sensed signals. When the output data is determined by the sense amplifier, an output logic level of the level sensor is inverted, and the sense amplifier is disabled. The sense amplifier is kept disabled until the next clock signal is generated, and no feedthrough current flows during this period, decreasing wasteful power cur­rent consumption.

Inventors

• 👤 Yutaka C/O Intellectual Property Div. Tanaka
• 👤 Masanori C/O Intellectual Property Div Haraguchi

Bibliographic Details