US4780686A
Expired / Lapsed
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Semiconductor differential amplifier
Assignee: Mitsubishi Electric Corp
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Filing: 1987-01-07
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Granted: 1988-10-25
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Expires: 2007-01-07
Abstract
Abstract A semiconductor differential amplifier includes first and second MOS transistors of a first conductivity type acting as driver transistors, and third through sixth MOS transistors of a second conductivity type acting as load transistors. First and second input terminals are respectively connected to gate terminals of the first and fifth, and second and sixth transistors. Therefore, since input signals are applied to transistors of both the load and driver sections of the amplifier, the amplifier exhibits a higher sensitivity for detecting relatively small differences between the voltage at the first input terminal and the voltage at the second input terminal.
Inventors
- 👤 Shuji Murakami
- 👤 Katsuki Ichinose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F2203/00; H03F2203/45; H03F2203/45112
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
151 words
A semiconductor differential amplifier, comprising: first and second MOS transistors of a first conductivity type having source terminals connected to a first constant voltage source; and third through sixth MOS transistors of a second conductivity type having source terminals connected to a second constant voltage source, gate terminals of said first and fifth MOS transistors being connected to a first input terminal, gate terminals of said second and sixth MOS transistors being connected to a second input terminal, drain terminals of said first, third and fifth MOS transistors and gate terminals of said third and fourth MOS transistors being connected to a common node, and drain terminals of said second, fourth and sixth MOS transistors being connected to an output terminal, wherein an output signal produced at said output terminal is represented of a voltage difference between first and second input signals applied to said first and second input terminals, respectively.
Claim 2
Dependent Claim
151 words
A semiconductor differential amplifier, comprising: first and second MOS transistors of a first conductivity type having source terminals connected to a first constant voltage source; and third through sixth MOS transistors of a second conductivity type having source terminals connected to a second constant voltage source, gate terminals of said first and fifth MOS transistors being connected to a first input terminal, gate terminals of said second and sixth MOS transistors being connected to a second input terminal, drain terminals of said first, third and fifth MOS transistors and gate terminals of said third and fourth MOS transistors being connected to a common node, and drain terminals of said second, fourth and sixth MOS transistors being connected to an output terminal, wherein an output signal produced at said output terminal is represented of a voltage difference between first and second input signals applied to said first and second input terminals, respectively.
Claim 3
Dependent Claim
53 words
The semiconductor differential amplifier of claim 1, further comprising a power-cut MOS transistor connected to said first constant voltage source and the source terminals of said first and second MOS transistors and a gate terminal coupled to receive a power-cut signal, to control the supply of power to said first through sixth transistors.
Claim 4
Dependent Claim
18 words
The semiconductor differential amplifier of claim 2, wherein said power-cut MOS transistor is of said first conductivity type.
Claim 5
Dependent Claim
18 words
The semiconductor differential amplifier of claim 2, wherein said power-cut MOS transistor is of said second conductivity type.
Claim 6
Dependent Claim
49 words
The semiconductor differential amplifier of claim 2, wherein the conductance factor ratios A1/A2, A3/A4 and A5/A6 are equal to each other, in which A i =the conductance factor of the i th MOS transistor=W/L, W=width of the gate of transistor i, L=length of the gate of transistor, and 1≦i≦6.
Claim 7
Dependent Claim
50 words
The semiconductor differential amplifier of claim 1, wherein the conductance factor ratios A1/A2, A3/A4 and A5/A6 are equal to each other, in which A i =the conductance factor of the i th MOS transistor=W/L, W=width of the gate of transistor i, L=length of the gate of transistor i, and 1≦i≦6.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-25 | 1992-04-25 | 1992-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-25 | 1996-04-25 | 1996-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-25 | 2000-04-25 | 2000-10-25 | $7700.00 | Window Closed / Lapsed |