CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range

Claim 2

A differential amplifier having an improved common-mode input-voltage range for providing common-mode rejection while providing differential-mode amplification through said extended range, comprising: a first, second, third, and fourth transistors coupled in series between a first voltage and a second voltage and having their gates coupled together to a junction of said second and third transistors which junction forming a bias node; a fifth, sixth, seventh, and eighth transistors also coupled in series said first voltage and said second voltage, and also having their gates coupled together to the gates of said first, second, third, and fourth transistors; a ninth transistor coupled between said first voltage and a first node; a tenth transistor coupled between a second node and said second voltage; said ninth and tenth transistors having their gates coupled together to the gates of said first, second, third, and fourth transistors; an eleventh transistor coupled between said first node and the junction of said third and fourth transistors; a twelfth transistor coupled between said second node and the junction of said first and second transistors; said eleventh and twelfth transistors having their gates coupled together to receive a first differential input signal; a thirteenth transistor coupled between said first node and a junction of said seventh and eighth transistors; a fourteenth transistor coupled between said second node and a junction of said fifth and sixth transistors; said thirteenth and fourteenth transistors having their gates coupled together to receive a second differential input signal; said biasing node providing a negative feedback in order to compensate for circuit variations; said biasing node also providing for common-mode rejection, but providing differential-mode amplification.

Claim 3

The differential amplifier of claim 1, wherein said first, second, third and fourth transistors are matched to said fifth, sixth, seventh and eighth transistors, respectively; and said eleventh transistor is matched to said thirteenth transistor and said twelfth transistor is matched to said fourteenth transistor.

Claim 4

The differential amplifier of claim 2, wherein said first and fourth transistors are complementary transistor pairs, said second and third transistors are complementary pairs, said fifth and eighth transistors are complementary pairs, said sixth and seventh transistors are complementary pairs, said eleventh and twelfth transistors are complementary pairs, said thirteenth and fourteenth transistors are complementary pairs and said ninth and tenth transistors are complementary pairs.

Claim 5

The differential amplifier of claim 3, wherein said second voltage is a ground having zero volts.

Claim 6

A complementary metal-oxide semiconductor (CMOS) complementary, self-biased, differential amplifier for providing rail-to-rail common-mode input-voltage range comprising; a first transistor having its source coupled to a positive supply rail; a second transistor having its source coupled to the drain of said first transistor and having its drain coupled to a biasing node; a third transistor having its drain coupled to said biasing node; a fourth transistor having its drain coupled to the source of said third transistor and its source coupled to a negative supply rail; said first, second, third and fourth transistors having their gates coupled to said biasing node; a fifth transistor having its source coupled to said positive supply rail; a sixth transistor having its source coupled to the drain of said fifth transistor and its drain coupled to an output node; a seventh transistor having its drain coupled to said output node; an eighth transistor having its drain coupled to the source of said seventh transistor and its source coupled to said negative supply rail; said fifth, sixth, seventh and eighth transistors having their gates coupled to said biasing node; a ninth transistor having is source coupled to said positive supply rail and its drain coupled to a first node; a tenth transistor having its drain coupled to a second node and its source coupled to said negative supply rail; said ninth and tenth transistors also having their gates coupled to said biasing node; an eleventh transistor having it source coupled to said first node and its drain coupled to the junction of said third and fourth transistors; a twelfth transistor having its source coupled to said second node and its drain coupled to the junction of said first and second transistors; said eleventh and twelfth transistors having their gates coupled to receive a first differential input signal; a thirteenth transistor having its source coupled to said first node and its drain coupled to the junction of said seventh and eighth transistors; a fourteenth transistor having its source coupled to said second node and its drain coupled to the junction of said fifth and sixth transistors; said thirteenth and fourteenth transistors having their gates coupled to receive a second differential input signal; said first, second, fifth, sixth, ninth, eleventh and thirteenth transistors being of p-type devices; said third, fourth, seventh, eighth, tenth, twelfth and fourteenth transistors being of n-type devices; wherein a negative feedback from said biasing node provides for low sensitivity to temperature, process, supply-voltage, common-mode input-voltage variations and further provides for improved common-mode rejection while providing differential-mode amplification.

Claim 7

A complementary metal-oxide semiconductor (CMOS) complementary, self-biased, differential amplifier for providing rail-to-rail common-mode input-voltage range comprising; a first transistor having its source coupled to a positive supply rail; a second transistor having its source coupled to the drain of said first transistor and having its drain coupled to a biasing node; a third transistor having its drain coupled to said biasing node; a fourth transistor having its drain coupled to the source of said third transistor and its source coupled to a negative supply rail; said first, second, third and fourth transistors having their gates coupled to said biasing node; a fifth transistor having its source coupled to said positive supply rail; a sixth transistor having its source coupled to the drain of said fifth transistor and its drain coupled to an output node; a seventh transistor having its drain coupled to said output node; an eighth transistor having its drain coupled to the source of said seventh transistor and its source coupled to said negative supply rail; said fifth, sixth, seventh and eighth transistors having their gates coupled to said biasing node; a ninth transistor having is source coupled to said positive supply rail and its drain coupled to a first node; a tenth transistor having its drain coupled to a second node and its source coupled to said negative supply rail; said ninth and tenth transistors also having their gates coupled to said biasing node; an eleventh transistor having it source coupled to said first node and its drain coupled to the junction of said third and fourth transistors; a twelfth transistor having its source coupled to said second node and its drain coupled to the junction of said first and second transistors; said eleventh and twelfth transistors having their gates coupled to receive a first differential input signal; a thirteenth transistor having its source coupled to said first node and its drain coupled to the junction of said seventh and eighth transistors; a fourteenth transistor having its source coupled to said second node and its drain coupled to the junction of said fifth and sixth transistors; said thirteenth and fourteenth transistors having their gates coupled to receive a second differential input signal; said first, second, fifth, sixth, ninth, eleventh and thirteenth transistors being of p-type devices; said third, fourth, seventh, eighth, tenth, twelfth and fourteenth transistors being of n-type devices; wherein a negative feedback from said biasing node provides for low sensitivity to temperature, process, supply-voltage, common-mode input-voltage variations and further provides for improved common-mode rejection while providing differential-mode amplification.

Claim 8

The differential amplifier of claim 5, wherein said first, second, third and fourth transistors are matched to said fifth, sixth, seventh and eighth transistors, respectively; and said eleventh transistor is matched to said thirteenth transistor and said twelfth transistor is matched to said fourteenth transistor.

Claim 9

The differential amplifier of claim 6, wherein said first and fourth transistors are complementary transistor pairs, said second and third transistors are complementary pairs, said fifth and eighth transistors are complementary pairs, said sixth and seventh transistors are complementary pairs, said eleventh and twelfth transistors are complementary pairs, said thirteenth and fourteenth transistors are complementary pairs and said ninth and tenth transistors are complementary pairs.

Claim 10

The differential amplifier of claim 7, wherein said negative supply rail is actually a ground having zero volts.