EP0407591B1
Expired / Lapsed
EP
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Differential amplifier circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1989-10-06
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Granted: 1996-08-21
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Expires: 2009-10-06
Abstract
Abstract A differential amplifier circuit that compares a potential difference between a first input (Ain) and a second input (Vr) to produce complementary output signals (A^¨B7, A). Potential drops of the output signals (A, A) are detected by fixing means that is constituted by n-channel FET's (33, 34) of which the drains are connected to nodes (N3, N4) of a flip-flop circuit (20) and of which the sources are connected to a second potential (Vss), and inverters (31, 32) of which the outputs are connected to the gates of the n-channel FET's (33, 34). Nodes (N3, N4) connected to nodes (N1, N2) that produce output signals (A, A^¨B7) are fixed to the second potential (Vss), in order to increase the speed of operation and to decrease the number of timing control signals (Ø).
Inventors
- 👤 Sanpei Oki Electric Industry Co. Ltd. Miyamoto
- 👤 Hidenori Oki Electric Industry Co. Ltd. Uehara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 12:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356165; H03K3/356113; H03K3/356147
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
341 words
A differential amplifier comprising: first (N1), second (N2), third (N3) and fourth (N4) nodes; a first transistor (24) of a first conductivity type having a first control electrode coupled to the first node (N1), said first transistor (24) being coupled between the second node (N2) and a source of a first potential (V CC ); a second transistor (23) of the first conductivity type having a second control electrode coupled to the second node (N2), the second transistor (23) being coupled between the first potential source (V CC ) and the first node (N1); a third transistor (25) of a second conductivity type having a third control electrode coupled to the second node (N2), the third transistor (25) being coupled between the first node (N1) and the third node (N3); a fourth transistor (26) of the second conductivity type having a fourth control electrode coupled to the first node (N1), the fourth transistor (26) being coupled between the second node (N2) and the fourth node (N4); a first potential defining circuit, having a first input terminal (A in ) and being coupled to the third node (N3), for defining a potential of the first node (N1) in response to a signal applied to the first input terminal (A in ); a second potential defining circuit, having a second input terminal (V r ) and being coupled to the fourth node (N4), for defining a potential of the second node (N2) in response to a signal applied to the second input terminal (V r ); a fifth transistor (33; 43) having a fifth control electrode and being coupled to a source of a second potential (V SS ; φ ¯ ) and to the third node (N3); and a potential detecting circuit for detecting the potential of the first node (N1) and causing the fifth transistor (33; 43) to be conductive when the potential of the first node (N1) is less than a middle potential between the first potential (V CC ) and the second potential (V SS ; φ ¯ ).
Claim 2
Dependent Claim
33 words
A differential amplifier according to claim 1 wherein the first transistor (24) and the second transistor (23) are p-channel FETs, and the third transistor (25) and the fourth transistor (26) are n-channel FETs.
Claim 3
Dependent Claim
54 words
A differential amplifier according to claim 1 wherein the first potential defining circuit comprises a sixth transistor (29) having a sixth control electrode coupled to the first input terminal (A in ), the sixth transistor (29) being coupled between the second potential source (V SS ; φ ¯ ) and the third node (N3).
Claim 4
Dependent Claim
16 words
A differential amplifier according to claim 3 wherein the sixth transistor (29) is an n-channel FET.
Claim 5
Dependent Claim
50 words
A differential amplifier according to claim 3 wherein the second potential defining circuit comprises a seventh transistor (30) having a control electrode coupled to the second input terminal (V r ), and being coupled between the second potential source (V SS ; φ ¯ ) and the fourth node (N4).
Claim 6
Dependent Claim
21 words
A differential amplifier according to claim 5 wherein said transistor (30) of said second potential defining circuit is an n-channel FET.
Claim 7
Dependent Claim
36 words
A differential amplifier according to claim 1 wherein said potential detecting circuit comprises an inverter (32) having an input terminal coupled to the first node (N1) and an output terminal coupled to the fifth control electrode.
Claim 8
Dependent Claim
66 words
A differential amplifier according to claim 5 further comprising: an eighth transistor (27) coupled between the third node (N3) and the sixth transistor (29) and having a control electrode to which an active signal (φ) is applied; and a ninth transistor (28) coupled between the fourth node (N4) and the seventh transistor (30) and having a control electrode to which the active signal (φ) is applied.
Claim 9
Dependent Claim
18 words
A differential amplifier according to claim 8 wherein said eighth (27) and ninth (28) transistors are n-channel FETs.
Claim 10
Dependent Claim
72 words
A differential amplifier according to claim 8 further comprising: a tenth transistor (21) coupled between the first potential source (V CC ) and the first node (N1), and having a control electrode to which the active signal (φ) is applied; and an eleventh transistor (22) coupled between the first potential source (V CC ) and the second node (N2), and having a control electrode to which the active signal (φ) is applied.
Claim 11
Dependent Claim
18 words
A differential amplifier according to claim 10 wherein said tenth (21) and eleventh (22) transistors are p-channel FETs.
Claim 12
Dependent Claim
92 words
A differential amplifier according to claim 10 further comprising: a twelfth transistor (34; 44) having a control electrode and being coupled between said second potential source (V SS ; φ ¯ ) and said fourth node (N4); and another potential detecting circuit for detecting the potential of the second node (N2) and causing said twelfth transistor (34; 44) to be conductive when the potential of the second node (N2) is less than the middle potential of the first potential (V CC ) and the second potential (V SS ; φ ¯ ).
Claim 13
Dependent Claim
42 words
A differential amplifier according to claim 12 wherein said another potential defining circuit comprises an inverter (31) having an input terminal coupled to the second node and having an output terminal coupled to the control electrode of said twelfth transistor (34; 44).
Claim 14
Dependent Claim
73 words
A differential amplifier according to claim 1 for an integrated circuit, characterized in that said first (24) and second (23) transistors are cross-coupled p-channel transistors and said third (25) and fourth (26) transistors are cross-coupled n-channel transistors, each having a respective path of controllable conductivity and a control electrode and being part of a Flip-Flop (20), whereby first and second nodes within said flip flop are providing output signals from the differential amplifier.
Claim 15
Dependent Claim
31 words
The amplifier of claim 14 wherein said potential detecting circuit includes: an inverter (32) having an input coupled to said first node and an output coupled to the fifth control electrode.
Claim 16
Dependent Claim
18 words
The amplifier of claim 14 further comprising a second voltage detection circuit coupled to said second node (N2).
Claim 17
Dependent Claim
77 words
The amplifier of claim 14 further including: third (21) and fourth (22) p-channel transistors, the third p-channel transistor (21) coupled between said first potential source (V CC ) and the first node (N1), the fourth p-channel transistor (22) coupled between said first potential source and the second node (N2); an input coupled to receive an active control signal (φ), said input coupling said control signal to control electrodes of said third (21) and fourth (22) p-channel transistors.
Claim 18
Dependent Claim
71 words
The amplifier of claim 14 wherein the first potential defining circuit comprises a third n-channel transistor (29) having a control electrode coupled to the first input terminal (A in ) to which the first input signal is applied, and the second potential defining circuit comprises a fourth n-channel transistor (30) having a control electrode coupled to the second input terminal (V r ) to which the second input signal is applied.
Claim 19
Dependent Claim
68 words
The amplifier of claim 18 further comprising: a fifth n-channel transistor (27) coupled between the third node (N3) and said first potential defining circuit and having a control electrode to which an active signal (φ) is applied; and a sixth n-channel transistor (28) coupled between the fourth node (N4) and said second potential defining circuit and having a control electrode to which the active signal (φ) is applied.
Claim 20
Dependent Claim
68 words
A differential amplifier according to claim 1 characterizd in that said transistors (23, 24, 25, 26) and a pair said of nodes (N1, N2) are part of a Flip-Flop (20); a pair of output terminals ( A ¯ , A) is coupled to said nodes (N1, N2), respectively; and in that a pull down circuit is responsively coupled between said potential detecting circuit and said flip flop (20).
Claim 21
Dependent Claim
36 words
The amplifier of claim 20 further including: a precharge circuit having a pair of pull up transistors and configured to pull up a voltage potential on said nodes (N1, N2) in response to a control signal.
Claim 22
Dependent Claim
40 words
A differential amplifier according to claim 12 for an integrated circuit wherein said potential detecting circuit comprises an inverter (32) having an input terminal coupled to said first node (N1) and an output terminal coupled to the fifth control electrode.
Claim 23
Dependent Claim
43 words
A differential amplifier according to claim 22 wherein said second potential detecting circuit comprises an inverter (31) having an input terminal coupled to the second node (N2) and having an output terminal coupled to the control electrode of said twelfth transistor (34; 44).
References Cited (Backward Citations)
US4910713A
Cited
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