Signal input circuit utilizing flip-flop circuit

Claim 2

A signal input circuit comprising a flip-flop circuit having first, second, third and fourth terminals, a first transistor supplied with an input signal voltage, a second transistor supplied with a reference voltage, a first gate having a control terminal connected to said third terminal of said flip-flop circuit, a second gate having a control terminal connected to said fourth terminal of said flip-flop circuit, a reference terminal, means for connecting said first transistor and said first gate in series between said first terminal of said flip-flop circuit and said reference terminal, means for connecting said second transistor and said second gate in series between said second terminal of said flip-flop circuit and said reference terminal, said flip-flop circuit amplifying a difference in potential between said first and second terminals caused by a difference between said input signal voltage and said reference voltage and thereby producing an enlarged potential difference between said first and second terminals, said flip-flop circuit further producing a first level and a second level at said third and fourth terminals, respectively, when said input signal voltage is larger than said reference voltage and said second level and said first level at said third and fourth terminals, respectively, when said input signal voltage is smaller than said reference voltage, each of said first and second gates taking an open state by said first level and a closed state by said second level, and means coupled to said first and second terminals of said flip-flop circuit and responsive to said enlarged potential difference for producing an output signal.

Claim 3

A transistor circuit comprising an activating terminal supplied with an activating signal, a reference terminal, first and second transistors connected in series between said activating terminal and said reference terminal, third and fourth transistors connected in series between said activating terminal and said reference terminal, first and second nodes, a fifth transistor connected between said first node and said reference terminal, a sixth transistor connected between said second node and said reference terminal, a first terminal connected to a connection point of said third and fourth transistors and control electrodes of said second and fifth transistors, a second terminal connected to a connection point of said first and second transistors and control electrodes of said fourth and sixth transistors, seventh and eighth transistors connected in series between said first terminal and said reference terminal, ninth and tenth transistors connected in series between said second terminal and said reference terminal, means for connecting said first node to a control electrode of said first transistor, means for connecting said second node to a control electrode of said third transistor, means for precharging said first and second nodes before said activating signal is supplied to said activating terminal, means for supplying a first voltage to a control electrode of said seventh transistor, means for supplying a second voltage to a control electrode of said ninth transistor, means for connecting said first node to a control electrode of said eighth transistor, and means for connecting said second node to a control electrode of said tenth transistor.

Claim 4

A transistor circuit comprising an activating terminal supplied with an activating signal, a reference terminal, first and second transistors connected in series between said activating terminal and said reference terminal, third and fourth transistors connected in series between said activating terminal and said reference terminal, first and second nodes, a fifth transistor connected between said first node and said reference terminal, a sixth transistor connected between said second node and said reference terminal, a first terminal connected to a connection point of said third and fourth transistors and control electrodes of said second and fifth transistors, a second terminal connected to a connection point of said first and second transistors and control electrodes of said fourth and sixth transistors, seventh and eighth transistors connected in series between said first terminal and said reference terminal, ninth and tenth transistors connected in series between said second terminal and said reference terminal, means for connecting said first node to a control electrode of said first transistor, means for connecting said second node to a control electrode of said third transistor, means for precharging said first and second nodes before said activating signal is supplied to said activating terminal, means for supplying a first voltage to a control electrode of said seventh transistor, means for supplying a second voltage to a control electrode of said ninth transistor, means for connecting said first node to a control electrode of said eighth transistor, and means for connecting said second node to a control electrode of said tenth transistor.

Claim 5

The circuit as claimed in claim 2, wherein said eighth transistor is connected between said first terminal and said seventh transistor and said tenth transistor is connected between said second terminal and said ninth transistor.

Claim 6

The circuit as claimed in claim 2, wherein said eighth transistor is connected between said seventh transistor and said reference terminal and said tenth transistor is connected between said ninth transistor and said reference terminal.

Claim 7

The circuit as claimed in claim 2, further comprising a third node, said seventh transistor being connected between said first terminal and said third node, said ninth transistor being connected between said second terminal and said third node, said eighth and tenth transistors being connected in series between said third node and said reference terminal.