US4458337A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer circuit
Assignee: Fujitsu Ltd
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Filing: 1982-03-03
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Granted: 1984-07-03
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Expires: 2002-03-03
Abstract
Abstract A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Shigeki Nozaki
- 👤 Tsutomu Mezawa
- 👤 Katsuhiko Kabashima
- 👤 Seiji Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:28
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
255 words
A buffer circuit, operatively connected to receive an external signal, first and second clock signals, and a reference voltage, for producing internal complementary outputs, comprising: a flip-flop having a first input/output terminal and a second input/output terminal and operatively connected to receive the second clock signal; a first input circuit, operatively connected to said first input/output terminal and operatively connected to receive the external signal and the first clock signal, said first input circuit activated by the first clock signal and comprising: a first transistor, operatively connected to said first input/output terminal, having a gate for receiving the first clock signal; and a second transistor, operatively connected in series with said first transistor, having a gate for receiving the external signal; a second input circuit operatively connected to said second input/output terminal and operatively connected to receive the reference voltage and the first clock signal, said second input circuit being activated by the first clock signal and comprising: a third transistor, operatively connected to said second input/output terminal, having a gate for receiving the first clock signal; and a fourth transistor, operatively connected in series with said third transistor, having a gate for receiving the reference voltage; an output circuit, operatively connected to said first and second input/output terminals, for producing complementary outputs upon receipt of the second clock signal by said flip-flop; and a first level setting device, operatively connected to the second input circuit, for supplying a voltage level to deactivate said second input circuit when said flip-flop receives the second clock signal.
Claim 2
Dependent Claim
255 words
A buffer circuit, operatively connected to receive an external signal, first and second clock signals, and a reference voltage, for producing internal complementary outputs, comprising: a flip-flop having a first input/output terminal and a second input/output terminal and operatively connected to receive the second clock signal; a first input circuit, operatively connected to said first input/output terminal and operatively connected to receive the external signal and the first clock signal, said first input circuit activated by the first clock signal and comprising: a first transistor, operatively connected to said first input/output terminal, having a gate for receiving the first clock signal; and a second transistor, operatively connected in series with said first transistor, having a gate for receiving the external signal; a second input circuit operatively connected to said second input/output terminal and operatively connected to receive the reference voltage and the first clock signal, said second input circuit being activated by the first clock signal and comprising: a third transistor, operatively connected to said second input/output terminal, having a gate for receiving the first clock signal; and a fourth transistor, operatively connected in series with said third transistor, having a gate for receiving the reference voltage; an output circuit, operatively connected to said first and second input/output terminals, for producing complementary outputs upon receipt of the second clock signal by said flip-flop; and a first level setting device, operatively connected to the second input circuit, for supplying a voltage level to deactivate said second input circuit when said flip-flop receives the second clock signal.
Claim 3
Dependent Claim
42 words
A buffer circuit as set forth in claim 1, further comprising a second level setting device, operatively connected to said first input circuit, for supplying a voltage level to deactivate said first input circuit when said flip-flop receives the second clock signal.
Claim 4
Dependent Claim
96 words
A buffer circuit as set forth in claim 1, wherein said first level setting device comprises: a fifth transistor having a gate, having a drain operatively connected to receive the external signal, and having a source operatively connected to said gate of said second transistor and operatively connected to ground when said flip-flop receives the second clock signal; and a first capacitor having a first terminal operatively connected to said gate of said fifth transistor and having a second terminal operatively connected to said gate of said second transistor and said source of said fifth transistor.
Claim 5
Dependent Claim
96 words
A buffer circuit as set forth in claim 2, wherein said second level setting device comprises: a sixth transistor having a gate, having a drain operatively connected to receive the reference voltage, and having a source operatively connected to said gate of said fourth transistor and operatively connected to ground when said flip-flop receives the second clock signal and a second capacitor having a first terminal operatively connected to said gate of said sixth transistor and having a second terminal operatively connected to said gate of said fourth transistor and said source of said sixth transistor.
Claim 6
Dependent Claim
74 words
A buffer circuit as set forth in claim 3, further comprising a seventh transistor having a gate operatively connected to receive the second clock signal, and having a drain and a source, either of which is operatively connected to ground, wherein said flip-flop is operatively connected to said seventh transistor, said seventh transistor selectively connecting said flip-flop and said first terminal of said first capacitor to ground upon receipt of the second clock signal.
Claim 7
Dependent Claim
74 words
A buffer circuit as set forth in claim 4, further comprising a seventh transistor having a gate operatively connected to receive the second clock signal, and having a drain and a source, either of which is operatively connected to ground, wherein said flip-flop is operatively connected to said seventh transistor, said seventh transistor selectively connecting said flip-flop and said first terminal of said second capacitor to ground upon receipt of the second clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |