Digitally controlled monolithic active phase shifter apparatus having a cascode configuration

Claim 2

A digitally controlled active phase shifter apparatus operative to shift the phase of a signal within a given frequency range as applied to an input terminal between 0-90 degrees at an output terminal, comprising: phase bit means having an input adapted to receive said input signal to provide at an output a signal shifted in phase by a given phase angle, active power divider means having an input coupled to said output of said phase bit means, said power divider including first and second power divider paths, each path including a plurality of cascode FET devices, with each device comprising a first FET arranged in a cascode stage configuration with a second common gate FET, with each of said first and second FET's having a gate electrode, a source electrode and a drain electrode, with the gate electrodes of said first FET's in each device connected together and coupled to said input of said power divider means and with the gate electrodes of said common gate FET's each adapted to receive a first control signal for selectively biasing each cascode stage ON or OFF, with the drain electrodes of said common gate FET's in said first path connected together to provide a first output of said power divide means and with the drain electrodes of said common gate FET's in said second path connected together to provide a second output of said power divider means, with the source electrodes of said first FET's in each device connected together to a point of reference potential, a pair of phase delay networks with a first one operative to provide a given fixed phase delay of a given polarity and having an input coupled to said first output of said power divider, and a second one operative to provide an opposite polarity given phase delay and having an input coupled to said second output of said power divider, each of said phase delay networks having a respective output, an active power combiner means having a first and second pair of FET's, each FET pair is in a cascode configuration with each FET having a gate electrode, a source electrode and a drain electrode with one FET in said first pair having the gate electrode coupled to said output of said first network and one FET in said second pair having the gate electrode coupled to said output of said second network with the source electrodes of said one FET's coupled to a point of reference potential with the other FET in each pair arranged in a common gate configuration and having the gate electrode adapted to receive a second control signal, with the drain electrodes of said common gate FET's coupled together to provide said output terminal for said phase shifter, digital control means coupled to said gate electrode of said common gate FET's of said power divider to select cascode stages of said power divider according to a desired phase shift to be implemented via said first and second paths, whereby said power combiner can combine said signals from said power divider to provide a phase shift for said input signal between 0-90 degrees at said output terminal.

Claim 3

The digitally controlled phase shifter according to claim 1, wherein said phase bit means includes a 90 degree phase bit in series with a 180 degree phase bit.

Claim 4

The digitally controlled phase shifter according to claim 2, wherein said 90 and 180 degree phase bits are bidirectional phase bits.

Claim 5

The digitally controlled phase shifter according to claim 1, wherein said gate electrodes of said common gate FET's in said combiner are coupled to a vernier control source to provide additional phase variation of the combined signal within said range of 0-90 degrees.

Claim 6

The digitally controlled phase shifter according to claim 1, wherein said pair of phase delay networks provide a given phase delay of +45 degrees for said first network and -45 degrees for said second network.

Claim 7

The digitally controlled active phase shifter apparatus according to claim 1, wherein certain of said cascode FET devices in said first and second paths have different gains than other of said devices in said first and second paths.

Claim 8

The digitally controlled active phase shifter apparatus according to claim 1, wherein first selected ones of said cascode FET devices in said active power divider means include first and second FET's each having a given gate width, and wherein other selected ones of said cascode FET devices include first and second FET's each having a different gate width than that of said first selected FET devices whereby said first selected devices have a different gain than said other selected devices.

Claim 9

The digitally controlled active phase shifter according to claim 1, wherein said phase bit means includes a first phase bit network for providing a first phase shift at a given angle at an output and a second phase bit network for providing a second phase shift at an angle which is the negative of said given angle, each of said phase bit networks having an input for receiving said input signal and an output for providing said phase shifted output signal, first switching means having a common terminal adapted to receive said input signal and a first terminal coupled to said input terminal of said first network and a second terminal coupled to said input terminal of said second network whereby said input signal can be selectively applied to said first or said second network.

Claim 10

The digitally controlled active phase shifter according to claim 8, further including, second switching means having a common terminal coupled to the input of said active divider means and a first terminal coupled to the output of said first network and a second terminal coupled to the output of said second network whereby the output of said first or second network can be selectively applied to the input of said active divider means.

Claim 11

A digitally controlled active phase shifter apparatus operative to shift the phase of a signal within a given frequency range as applied to an input terminal between 0-360 degrees at an output terminal, comprising: a 90 degree phase bit having said input terminal adapted to receive said signal to provide at a first output a signal with a phase shift of 30 45 degrees and at a second output a signal with a phase shift of -45 degrees, first switching means coupled to said first and second outputs to select either said first or second output signals at an output terminal of said first switching means, a 180 degree phase bit having an input coupled to said first switching means output and operative to provide at a first output a signal with a phase shift of +90 degrees and at a second output a signal with a phase shift of -90 degrees second switching means coupled to said first and second outputs of said 180 degree phase bit to select either said first or second output signals at an output of said second switching means, an active power divider means having an input coupled to said output of said second switching means, said power divider including first and second power divider paths, each path including a plurality of cascode FET devices, with each device in said plurality including a first FET arranged in a cascode configuration with a second common gate FET, with each of said first and second FET's having a gate electrode, a source electrode and a drain electrode, with the gate electrodes of said first FET's connected together and coupled to said output of said second switching means and with the gate electrodes of said common gate FET's each adapted to receive a first control signal, to selectively bias each cascode stage ON or OFF, with the drain electrodes of said common gate FET's in said first and second paths connected together to form a first output for said first path and a second output for said second path, and with the source electrodes of said first FET's in each device connected together to a point of reference potential, a pair of phase delay networks with a first one operative to provide a +45 degree phase delay and having an input coupled to said output of said first path, and a second one operative to provide a -45 degree phase delay having an input coupled to said output of said second path, each of said phase delay networks having a respective output, an active power combiner means having a first and a second pair of FET's each FET pair is in a cascode configuration with each FET having a gate electrode, a source electrode and a drain electrode, with one FET in said first pair having the gate electrode coupled to the output of said first phase delay network, and with one FET in said second pair having the gate electrode coupled to the output of said second phase delay network, with the source electrodes of said one FET's coupled to a point of reference potential, with the other FET in each pair arranged in a common gate configuration and having the gate electrodes of said common gate FET adapted to receive a second control signal to provide additional phase variation, with the drain electrodes of said common gate FET's coupled together to provide said output terminal for said phase shifter, digital control means coupled to said gate electrodes of said common gate FET's of said power divider for providing said first control signal to select cascode stages of said power divider according to a desired phase shift to be implemented via said first and second path, and control means coupled to said gate electrodes of said common gate FET's in said active power combiner to provide said second control signal to combine said signals from said first and second paths, whereby said input signal can be selectively phase shifted from 0-90 degrees at said output terminal.

Claim 12

A digitally controlled active phase shifter apparatus operative to shift the phase of a signal within a given frequency range as applied to an input terminal between 0-360 degrees at an output terminal, comprising: a 90 degree phase bit having said input terminal adapted to receive said signal to provide at a first output a signal with a phase shift of 30 45 degrees and at a second output a signal with a phase shift of -45 degrees, first switching means coupled to said first and second outputs to select either said first or second output signals at an output terminal of said first switching means, a 180 degree phase bit having an input coupled to said first switching means output and operative to provide at a first output a signal with a phase shift of +90 degrees and at a second output a signal with a phase shift of -90 degrees second switching means coupled to said first and second outputs of said 180 degree phase bit to select either said first or second output signals at an output of said second switching means, an active power divider means having an input coupled to said output of said second switching means, said power divider including first and second power divider paths, each path including a plurality of cascode FET devices, with each device in said plurality including a first FET arranged in a cascode configuration with a second common gate FET, with each of said first and second FET's having a gate electrode, a source electrode and a drain electrode, with the gate electrodes of said first FET's connected together and coupled to said output of said second switching means and with the gate electrodes of said common gate FET's each adapted to receive a first control signal, to selectively bias each cascode stage ON or OFF, with the drain electrodes of said common gate FET's in said first and second paths connected together to form a first output for said first path and a second output for said second path, and with the source electrodes of said first FET's in each device connected together to a point of reference potential, a pair of phase delay networks with a first one operative to provide a +45 degree phase delay and having an input coupled to said output of said first path, and a second one operative to provide a -45 degree phase delay having an input coupled to said output of said second path, each of said phase delay networks having a respective output, an active power combiner means having a first and a second pair of FET's each FET pair is in a cascode configuration with each FET having a gate electrode, a source electrode and a drain electrode, with one FET in said first pair having the gate electrode coupled to the output of said first phase delay network, and with one FET in said second pair having the gate electrode coupled to the output of said second phase delay network, with the source electrodes of said one FET's coupled to a point of reference potential, with the other FET in each pair arranged in a common gate configuration and having the gate electrodes of said common gate FET adapted to receive a second control signal to provide additional phase variation, with the drain electrodes of said common gate FET's coupled together to provide said output terminal for said phase shifter, digital control means coupled to said gate electrodes of said common gate FET's of said power divider for providing said first control signal to select cascode stages of said power divider according to a desired phase shift to be implemented via said first and second path, and control means coupled to said gate electrodes of said common gate FET's in said active power combiner to provide said second control signal to combine said signals from said first and second paths, whereby said input signal can be selectively phase shifted from 0-90 degrees at said output terminal.

Claim 13

The digitally controlled phase shifter according to claim 10, wherein said input signal is in a frequency range between 8-11 GHz.

Claim 14

The digitally controlled active phase shifter according to claim 10, wherein said FET's in said power divider and power combiner are MESFET's.

Claim 15

The digitally controlled active phase shifter according to claim 10, wherein 90 degree phase bit is a passive network having a first all pass LC network for providing a phase shift at said first output of +45 degrees and a second all pass LC network for providing a phase shift at said second output of -45 degrees.

Claim 16

The digitally controlled active phase shifter according to claim 13, wherein said inputs of said first and second all pass networks are coupled respectively to a first terminal and a second terminal of a single pole double throw switch having a common terminal coupled to said input terminal to receive said input signal.

Claim 17

The digitally controlled active phase shifter according to claim 14, wherein said SPDT switch includes FET devices each having a source electrode, a drain electrode and a gate electrode with one FET having a source-to-drain path in series between said first and common terminals and a second FET having a source to drain path in series between said second and common terminals, and means coupled to said gate electrodes of said first and second FET's to bias one ON while the other is OFF to thereby couple either said first or second terminal to said common terminal.

Claim 18

The digitally controlled active phase shifter according to claim 10, wherein said first switching means is an SPDT switch having a first switch terminal coupled to said first output of said 90 degree phase bit and a second switch terminal coupled to said second output of said 90 degree phase bit, with a common switch terminal of said SPDT switch coupled to the input of said 180 degree phase bit.

Claim 19

The digitally controlled active phase shifter according to claim 10, wherein said 180 degree phase bit includes a first all pass LC network for providing a +90 degree phase shift at said first output of said 180 degree phase bit and a second all pass LC network for providing a -90 degree phase shift at said second output of said 180 degree phase bit, said first and second all pass networks each having a separate input and third switching means coupled to said inputs of said first and second all pass networks for applying either of said first or second outputs of said first switching means to the input of either said first or second all pass networks.

Claim 20

The digitally controlled active phase shifter according to claim 10, wherein certain of said FET's in said cascode devices have different gain factors than other cascode devices to thereby obtain different signal amplitudes depending upon which cascode devices are selected by said digital control means.

Claim 21

The digitally controlled active phase shifter according to claim 18, wherein first selected ones of said cascode FET devices in said active power divider means include first and second ET's each having a given gate width, and wherein other selected ones of said cascode FET devices include first and second FET's each having a different gate width than that of said first selected FET devices whereby said first selected devices have a different gain than said other selected devices.

Claim 22

The digitally controlled active phase shifter apparatus according to claim 18, wherein each FET as arranged in said common gate configuration has the gate electrode bypassed for input signal frequencies by a capacitor which is connected between said gate electrode and a point of reference potential.

Claim 23

The digitally controlled active phase shifter apparatus according to claim 18, wherein said FET's are N-channel MESFET's fabricated on a GaAs substrate.

Claim 24

The digitally controlled phase shifter according to claim 10, wherein said power divider has five cascode devices in said first path and five cascode devices in said second path.

Claim 25

The digitally controlled 5 bit phase shifter according to claim 10, wherein said phase shifter provides a phase shift between 0-90 degrees at 11.25 degree increments.

Claim 26

The digitally controlled 6 bit phase shifter according to claim 10, wherein said phase shifter provides a phase shift between 0-90 degrees at 5.625 degree increments.

Claim 27

The digitally controlled phase shifter according to claim 10, wherein said 90 degree phase bit, said first switching means, said 180 degree phase bit, said second switching means, said active power divider means, said pair of phase delay networks and said active power combiner means are all fabricated on a single Gaas substrate employing MMIC techniques.

Claim 28

The digitally controlled active phase shifter apparatus according to claim 10, wherein said 90 degree phase bit is a bidirectional phase bit.

Claim 29

The digitally controlled active phase shifter apparatus according to claim wherein said 180 degree phase bit is a bidirectional phase bit.