US4870303A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase detector
Assignee: NXP USA Inc
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Filing: 1988-06-03
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Granted: 1989-09-26
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Expires: 2008-06-03
Abstract
Abstract A detection circuit for providing an error signal corresponding to the phase difference between applied input signals is described comprising a balanced multiplier input section for receiving the input signals and having a pair of outputs; a first switching circuit responsive to a switching signal for commutating the outputs of the multiplier section between first and second circuit nodes; a current turnaround circuit coupled between the first and second circuit nodes and third and fourth circuit nodes, a second switching circuit responsive to the switching signal for alternately coupling the third and fourth circuit nodes to a fifth circuit node and an output of the detection circuit; a current mirror circuit having first and second terminals and a third switching circuit responsive to the switching signal for alternately coupling the first and second terminals of the current mirror circuit to the fifth circuit node and the output of the detection circuit.
Inventors
- 👤 Michael McGinn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:22
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/02; H03D13/00; H03D13/007; H03D13/008; H03D2200/00; H03D2200/0001; H03D2200/0009; H03D2200/0033; H03D2200/0041; H03D2200/0047
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
138 words
A phase detector, comprising: a balanced multiplier section having inputs and a pair of outputs; first switching circuit means responsive to a switching signal for alternately coupling said pair of outputs of said multiplier section between first and second circuit nodes respectively; a current turn-around circuit coupled between said first and second current nodes and third and fourth circuit nodes; second switching circuit means responsive to said switching signal for alternately coupling said third and fourth circuit nodes between fifth and sixth circuit nodes respectively; a current mirror having first and second current conduction paths; third switching circuit means responsive to said switching signal for alternately coupling said first and second current conduction paths between said sixth and fifth circuit nodes respectively; and circuit means for coupling said fifth circuit node to an output of the phase detector.
Claim 2
Dependent Claim
138 words
A phase detector, comprising: a balanced multiplier section having inputs and a pair of outputs; first switching circuit means responsive to a switching signal for alternately coupling said pair of outputs of said multiplier section between first and second circuit nodes respectively; a current turn-around circuit coupled between said first and second current nodes and third and fourth circuit nodes; second switching circuit means responsive to said switching signal for alternately coupling said third and fourth circuit nodes between fifth and sixth circuit nodes respectively; a current mirror having first and second current conduction paths; third switching circuit means responsive to said switching signal for alternately coupling said first and second current conduction paths between said sixth and fifth circuit nodes respectively; and circuit means for coupling said fifth circuit node to an output of the phase detector.
Claim 3
Dependent Claim
180 words
The phase detector of claim 1 wherein said first switching circuit means includes: first and second transistors each having a base, an emitter and a collector, said emitters being coupled to a first one of said pair of outputs of said multiplier section, said base of said first transistor being coupled to a first terminal and said base of said second transistor being coupled to a second terminal, said switching signal being applied across said first and second terminals; third and fourth transistors each having a base, an emitter and a collector, said emitters being coupled to a second one of said pair of outputs of said multiplier section, said collector of said third transistor being coupled with said collector of said first transistor to said first circuit node, said collector of said fourth transistor being coupled with said collector of said second transistor to said second circuit node, said bases of said third and fourth transistors being coupled respectively to said second and said first terminals; and said switching signal being supplied across said first and said second terminals.
Claim 4
Dependent Claim
141 words
The phase detector of claim 2 wherein said second switching circuit means includes; fifth and sixth transistors each having a base, an emitter and a collector, said emitters being coupled to said third circuit node, said base of said fifth transistor being coupled to said first terminal and said base of said sixth transistor being coupled to said second terminal; and seventh and eighth transistors each having a base, an emitter and a collector, said emitters being coupled to said fourth circuit node, said collector of said seventh transistor being coupled with said collector of said fifth transistor to said sixth circuit node, said collector of said eighth transistor being coupled with said collector of said sixth transistor to said fifth circuit node, said bases of said seventh and eighth transistors being coupled respectively to said second and said first terminals.
Claim 5
Dependent Claim
151 words
The phase detector of claim 3 wherein said third switching circuit means includes: ninth and tenth transistors each having a base, an emitter and a collector, said emitters being coupled to said second current conduction path of said current mirror, said base of said ninth transistor being coupled to said second terminal and said base of said tenth transistor being coupled to said first terminal; and eleventh and twelfth transistors each having a base, an emitter and a collector, said emitters being coupled to said first current conduction path of said current mirror, said collector of said eleventh transistor being coupled with said collector of said ninth transistor to said sixth circuit node, said collector of said twelfth transistor being coupled with said collector of said tenth transistor to said fifth circuit node, said bases of said eleventh and twelfth transistors being coupled respectively to said first and said second terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |