Phase synchronization pull-in system in bit error detecting apparatus

Claim 1

A phase synchronization pull-in system which is used in a bit error detecting apparatus, comprising: a monitored circuit for inputting an input signal, and processing said input signal, when an operation of said monitored circuit is to be monitored; a standard circuit, operatively connected to said monitored circuit for inversely processing an output of said monitored circuit with respect to the processing in said monitored circuit; a phase synchronization circuit, operatively connected to said monitored circuit, including a variable delay circuit for inputting said input signal of said monitored circuit, and adjusting a first delay time of the input signal so that the first delay time coincides with a second delay time of the output of said standard circuit corresponding to the input signal, the second delay time is obtained by inputting the input signal through said monitored circuit and said standard circuit; a bit error detecting circuit, operatively connected to said phase synchronization circuit and said variable delay circuit, for detecting a difference between said input signal after being delayed by said variable delay circuit, and the output of said standard circuit, bit by bit; and a controller, operatively connected to said phase synchronization circuit and said bit error detecting circuit, for controlling said adjusting of said first delay time, a monitoring operation of said monitored circuit, and a phase synchronization pull-in operation, using said phase synchronization circuit and said bit error detecting circuit, said phase synchronization pull-in operation is an operation for obtaining said first delay time which coincides with said second delay time output from said standard circuit corresponding to the input signal in said phase synchronization circuit, based on whether a bit error rate measured by setting the delay time is higher than a predetermined value; said first delay time of said phase synchronization circuit being changed within a predetermined range between a maximum delay value which is larger than an estimated maximum amount of said second delay time, and a minimum delay value which is less than an estimated minimum amount of said second delay time; and during said phase synchronization pull-in operation, said controller determines whether more than one of all possible values of said first delay time enables a successful phase synchronization pull-in, and carries out said monitoring operation when a successful phase synchronization pull-in is successfully carried out for only one of all possible values of said first delay time.