US4961013A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for generation of scan control signals for initialization and diagnosis of circuitry in a computer
Assignee: HP Inc
•
Filing: 1989-10-18
•
Granted: 1990-10-02
•
Expires: 2009-10-18
Abstract
Abstract A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.
Inventors
- 👤 John R. Obermeyer, Jr.
- 👤 John F. Shelton
- 👤 Donald A. Williamson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318572
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
131 words
A circuit for controlling scan data with reduced numbers of scan control lines, said circuit comprising: a delay line; a two-input multiplexer for system data and scan data; a first clocked latch; and a first OR gate; said delay line being coupled to receive a first clock input signal to produce a delayed first clock output signal, said first OR gate being coupled to receive said delayed first clock output signal and said first clock input signal to yield a scan mode enable signal; said multiplexer being coupled to receive as a control input said scan mode enable signal from said first OR gate; and said first clock latch having a data input coupled to a data output of said multiplexer and a strobe input coupled to receive a clock signal.
Claim 2
Dependent Claim
131 words
A circuit for controlling scan data with reduced numbers of scan control lines, said circuit comprising: a delay line; a two-input multiplexer for system data and scan data; a first clocked latch; and a first OR gate; said delay line being coupled to receive a first clock input signal to produce a delayed first clock output signal, said first OR gate being coupled to receive said delayed first clock output signal and said first clock input signal to yield a scan mode enable signal; said multiplexer being coupled to receive as a control input said scan mode enable signal from said first OR gate; and said first clock latch having a data input coupled to a data output of said multiplexer and a strobe input coupled to receive a clock signal.
Claim 3
Dependent Claim
172 words
A circuit for controlling scan data in a level sensitive scan design, said circuit comprising: a delay line; a two-input multiplexer for system data and scan data; a first clocked latch; a second clocked latch; and a first OR gate; said delay line being coupled to receive a first clock input signal to produce a delayed first clock output signal, said first OR gate being coupled to receive said delayed first clock output and said first clock input signal to yield a scan mode enable signal; said multiplexer being coupled to receive as a control input said scan mode enable signal from said first OR gate; said first clock latch having a data input coupled to a data output of said multiplexer and a strobe input coupled to receive a first clock signal including an A clock signal; and said second latch, having a data input coupled to receive data output of said first clock latch and a strobe input coupled to receive a second clock signal including a B clock signal.
Claim 4
Dependent Claim
172 words
A circuit for controlling scan data in a level sensitive scan design, said circuit comprising: a delay line; a two-input multiplexer for system data and scan data; a first clocked latch; a second clocked latch; and a first OR gate; said delay line being coupled to receive a first clock input signal to produce a delayed first clock output signal, said first OR gate being coupled to receive said delayed first clock output and said first clock input signal to yield a scan mode enable signal; said multiplexer being coupled to receive as a control input said scan mode enable signal from said first OR gate; said first clock latch having a data input coupled to a data output of said multiplexer and a strobe input coupled to receive a first clock signal including an A clock signal; and said second latch, having a data input coupled to receive data output of said first clock latch and a strobe input coupled to receive a second clock signal including a B clock signal.
Claim 5
Dependent Claim
88 words
The scan control circuit according to claim 2 further including: a first OR gate coupled to receive a first system clock signal and said A clock signal and to provide alternately said first system clock signal and said A clock signal to said strobe input of said first latch; and a second OR gate coupled to receive a second system clock signal and said B clock signal and to provide said second system clock signal or said B clock signal to said strobe input of said first latch.
Claim 6
Dependent Claim
225 words
A circuit for controlling scan data in a level sensitive scan design, said circuit comprising: a delay line; a multiplexer; a first latch; a second latch; a first AND gate; and a second AND gate; said delay line having a first delay output and a second delay output, said delay line having an input for a scan clock whose duration is longer than the duration of propagation in said first delay output; said delay line having its second delay output coupled to a scan mode enable input control of said multiplexer; said first latch having a data input coupled to a data output of said first multiplexer and strobe input coupled to receive a first clock signal including an A clock signal; said second latch having a data input coupled to receive data output of said first latch and a strobe input coupled to receive a second clock signal including a B clock signal; said first AND gate having a first input coupled to said first delay output and a second input coupled to receive an inverted representation of said scan clock, for producing said A clock signal; and said second AND gate being coupled to receive as one input said scan clock and as a second input an inverted representation of said first delay output of said scan clock to produce said B clock.
Claim 7
Dependent Claim
225 words
A circuit for controlling scan data in a level sensitive scan design, said circuit comprising: a delay line; a multiplexer; a first latch; a second latch; a first AND gate; and a second AND gate; said delay line having a first delay output and a second delay output, said delay line having an input for a scan clock whose duration is longer than the duration of propagation in said first delay output; said delay line having its second delay output coupled to a scan mode enable input control of said multiplexer; said first latch having a data input coupled to a data output of said first multiplexer and strobe input coupled to receive a first clock signal including an A clock signal; said second latch having a data input coupled to receive data output of said first latch and a strobe input coupled to receive a second clock signal including a B clock signal; said first AND gate having a first input coupled to said first delay output and a second input coupled to receive an inverted representation of said scan clock, for producing said A clock signal; and said second AND gate being coupled to receive as one input said scan clock and as a second input an inverted representation of said first delay output of said scan clock to produce said B clock.
Claim 8
Dependent Claim
88 words
The scan control circuit according to claim 4 further including: a first OR gate coupled to receive a first system clock signal and said A clock signal and to provide alternately said first system clock signal and said A clock signal to said strobe input of said first latch; and a second OR gate coupled to receive a second system clock signal and said B clock signal and to provide said second system clock signal or said B clock signal to said strobe input of said first latch.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-01 | 1994-04-02 | 1994-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-01 | 1998-04-02 | 1998-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-01 | 2002-04-02 | 2002-10-02 | $7700.00 | Window Closed / Lapsed |