Phase synchronization circuit

Claim 1

A phase synchronization circuit for generating an output signal which is synchronized with a reference signal, said circuit comprising: a delay circuit portion for delaying a clock signal, said delay circuit portion having a plurality of taps, said delay circuit producing delayed clock signals in sequence having different phases from said plurality of taps; and a selection circuit portion being connected to said plurality of taps of said delay circuit portion, said selection circuit portion for selecting one of a plurality of outputs from said plurality of taps, said selection circuit portion including a plurality of adjacent selection circuit units, each selection circuit unit comprises, a set/reset circuit having set and reset inputs and an output, a first gate circuit having a first input terminal connected with one of said plurality of taps, a second input terminal connected with another of said plurality of taps, a third input terminal for receiving said reference signal and an output terminal connected with the set input of said set/reset circuit, said first gate circuit supplying said set/reset circuit with a set signal when the inputs to said input terminals form a predetermined relationship, a second gate circuit having an input for receiving the output of said set/reset circuit and having another input for receiving the output of one of said delayed clock signals, wherein said set/reset circuit in a preceeding selection circuit unit of adjacent selection circuit units is reset by an output from said second gate circuit in a following selection circuit unit, said synchronization circuit operating such that, when a potential of said reference signal has a first binary value a set operation followed by a reset operation of said set/reset circuits is carried successively in accordance with the transmission of said clock signal along said delay circuit portion, and when the potential of said reference signal is changed to a second binary value, set/reset circuits, other than said set/reset circuit which was set immediately before said change of potential, are maintained in a reset state so that said delayed clock signal of a corresponding tap of said delay circuit portion is delivered to said output signal through said second gate circuit which receives the output of said set/reset circuit which is set immediately before said change of potential.